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radeonsi: disable the L2 cache for CPU read mappings of buffers

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for faster copying over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
This commit is contained in:
Marek Olšák 2020-05-06 14:51:50 -04:00 • committed by Marge Bot
parent 7356144fe4
commit c45a2145f5
1 changed files with 3 additions and 2 deletions
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5
src/gallium/drivers/radeonsi/si_buffer.c
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@ -479,8 +479,9 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour
struct si_resource *staging;
assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_TRANSFER_THREAD_SAFE)));
staging = si_resource(pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_STAGING,
box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT)));
staging = si_aligned_buffer_create(ctx->screen, SI_RESOURCE_FLAG_UNCACHED,
PIPE_USAGE_STAGING,
box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256);
if (staging) {
/* Copy the VRAM buffer to the staging buffer. */
si_sdma_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT,