Commit graph

29106 commits

Author SHA1 Message Date
Marek Olšák
ecf045b4f7 winsys/amdgpu: allocate FMASK properly
I expect no change in behavior, because r600_texture.c forces the same
tile mode as the base texture has.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
24faeb94be gallium/radeon: print tiling index when printing texture info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
37659071b8 gallium/radeon: don't do (fmask.size && cmask.size)
fmask implies that cmask is present too.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
2664351dfe gallium/radeon: re-order radeon_surf::dcc and htile members
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
2a2e537577 gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment
these names were misleading.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
67a44c97af gallium/radeon: remove flags specific to libdrm_radeon from winsys interface
These just say whether libdrm can assume that the latest radeon_surface
definition is used by Mesa.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
7a706ad25c gallium/radeon: remove r600_htile_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
7e73ff87c0 gallium/radeon: remove unnecessary fields from radeon_surf_level
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
d5c7ea3b83 gallium/radeon: decrease the size of radeon_surf
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
e9590d9092 gallium/radeon: pass pipe_resource and other params to surface_init directly
This removes input-only parameters from the radeon_surf structure.

Some of the translation logic from pipe_resource to radeon_surf is moved to
winsys/radeon.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
8b94976df9 radeon/vce: use nblk_y instead of npix_y
npix_y will be removed. level[0].npix_y will be removed too. nblk_y should
be the same as npix_y if the block height == 1. However, nblk_y is aligned
to the tile size, so it can be greater than npix_y.

If that's a problem, we'll have to save the input height of surface_init
and use that.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
ba174b8dff gallium/radeon: define RADEON_SURF_MODE_* as enums
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
b5118fe054 gallium/radeon: stop using some input fields from radeon_surface
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
28d237d63d gallium/radeon: fold r600_setup_surface into r600_init_surface
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
b0d8a717a7 winsys/amdgpu: remove unused definitions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
81a95946da gallium/radeon: fold radeon_winsys::surface_best into radeon/winsys
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
dc6bbe2dd0 gallium/radeon: use r600_gfx_write_event_eop everywhere
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
462e3cdf3b gallium/radeon: make r600_gfx_write_fence more generic
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
edf56fb428 gallium/radeon: fix a ZPASS comment, EVENT_WRITE_EOP fixups
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
d883c83ba9 radeonsi: enable SDMA on Carrizo and all CIK chips again
SDMA might be fixed by:
  "winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures"

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
6ec3b2a4b1 winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures
Maybe this is why SDMA has been broken for many amdgpu users?

SDMA is the only block which is used with imported textures and relies
on this variable. DB also uses it, but it doesn't get imported textures,
so it's unaffected.

I do get SDMA failures on Tonga before this patch if R600_DEBUG=testdma
is changed to use imported textures.

Cc: 11.2 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
dce05b3423 gallium/radeon: make sure the address of separate CMASK is aligned properly
This should fix random GPU hangs on Hawaii and Fiji.

Cc: 11.2 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Marek Olšák
8a21f52d73 gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_mode
Oh my god, I wonder what catastrophic issues this was causing on SI.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-26 13:02:58 +02:00
Timothy Arceri
e1af20f18a nir/i965/anv/radv/gallium: make shader info a pointer
When restoring something from shader cache we won't have and don't
want to create a nir_shader this change detaches the two.

There are other advantages such as being able to reuse the
shader info populated by GLSL IR.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-10-26 14:29:36 +11:00
Karol Herbst
0404678c5f nv50/ir: start LocalCSE with getFirst to merge PHI instructions
total instructions in shared programs : 3499888 -> 3499445 (-0.01%)
total gprs used in shared programs    : 453866 -> 453803 (-0.01%)
total local used in shared programs   : 21621 -> 21621 (0.00%)
total bytes used in shared programs   : 32078952 -> 32074936 (-0.01%)

                local        gpr       inst      bytes
    helped           0          39         119         119
      hurt           0           0           0           0

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-25 20:55:07 +02:00
Samuel Pitoiset
7b2712c367 nvc0: use correct bufctx when invalidating CP textures
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
2016-10-25 20:22:05 +02:00
Brian Paul
76c3f1bbbe gallium/stapi: fix comment for st_visual::buffer_mask
Trivial.
2016-10-24 17:22:00 -07:00
Brian Paul
88a618ce86 tgsi: trivial build fix for MSVC
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-24 14:16:07 -07:00
Samuel Pitoiset
6dbb8d12a8 nv50/ir: do not perform global membar for shared memory
Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-24 22:51:54 +02:00
Axel Davy
eed605a473 st/nine: Fix locking CubeTexture surfaces.
Only one face of Cubetextures was locked when in DEFAULT Pool.
Fixes:
https://github.com/iXit/Mesa-3D/issues/129

CC: "12.0 13.0" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
fe7bb46134 st/nine: Fix mistake in Volume9 UnlockBox
In the format fallback path,
the height was used instead of the depth.

CC: "12.0 13.0" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
942778099e st/nine: Use align_calloc instead of align_malloc
We are not sure exactly what needs to be 0 initialized,
but we are missing some cases. 0 initialize all our current
aligned allocation.

Fixes Tree of Savior visual issues.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
54010cf8b6 gallium/util: Add align_calloc
Add implementation for align_calloc,
which is align_malloc + memset.

v2: add if (ptr) before memset.
Fix indentation.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:56:44 +02:00
Axel Davy
25beccb379 st/nine: Fix leak with integer and boolean constants
Leak introduced by:
a83dce0128

The patch also moves the part to
release changed.vs_const_i and changed.vs_const_b
before the if (!cb.buffer_size) check,
to avoid reuploading every draw call if
integer or boolean constants are dirty, but the shaders
use no constants.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
CC: "13.0" <mesa-stable@lists.freedesktop.org>
2016-10-24 21:56:44 +02:00
Marek Olšák
f35b1d156b tgsi/scan: scan texture offset operands
This seems important considering how much we depend on some of the flags.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:38 +02:00
Marek Olšák
a2f98dff14 tgsi/scan: move src operand processing into a separate function
the next commit will need this

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:36 +02:00
Marek Olšák
72267a25db tgsi/scan: get information about shader buffer usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:35 +02:00
Marek Olšák
d89890d000 tgsi/scan: handle indirect image indexing correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:33 +02:00
Marek Olšák
ac37720f51 tgsi/scan: don't treat RESQ etc. as memory instructions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:30 +02:00
Marek Olšák
f095a4eb17 tgsi/scan: get information about indirect 2D file access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:28 +02:00
Marek Olšák
965a5f1810 tgsi/scan: get information about indirect CONST access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:26 +02:00
Samuel Pitoiset
d588e4f192 nv50/ir: display OP_BAR subops in debug mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-24 18:53:45 +02:00
Ilia Mirkin
7b7eb7170d nv50/ir: it appears that OP_DISCARD can't take a join modifier
nvdisasm does not print a .S even though the bit is set.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-22 12:02:35 -04:00
Ilia Mirkin
adad576bfc nv50/ir: use levelZero for non-frag tex/txp ops
radeonsi also does the same thing. I suspect that this is likely to be a
no-op in reality, but it brings nouveau code closer to what the blob
produces. Plus it makes sense to not try to do auto-derivatives on this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-22 12:02:35 -04:00
Ilia Mirkin
3fdeb7c983 gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
This allows the driver to signal that it can't handle random
interleaving of attributes across buffers. This is required for
ARB_transform_feedback3, and it's initialized to whatever the previous
value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for nv50 where
it is disabled. Note that the proprietary drivers never expose
ARB_transform_feedback3 on any GT21x's (where nouveau previously did),
and after some effort I was unable to get it to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-22 12:02:35 -04:00
Samuel Pitoiset
6e08f3e96c nvc0/ir: remove outdated comment about SHLADD
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-22 14:50:17 +02:00
Eric Anholt
8ff4182876 vc4: Avoid making temporaries for assignments to NIR registers.
Getting stores to NIR regs to not generate new MOVs is tricky, since the
result we're trying to store into the NIR reg may have been from a
conditional update of a temp, or a series of packed writes.  The easiest
solution seems to be to require that nir_store_dest()'s arg comes from an
SSA temp.

This causes us to put in a few more temporary MOVs in the NIR SSA dest
case, but copy propagation successfully cleans those up.

The shader-db change is modest:

total instructions in shared programs: 93774 -> 93598 (-0.19%)
instructions in affected programs:     14760 -> 14584 (-1.19%)
total estimated cycles in shared programs: 212135 -> 211946 (-0.09%)
estimated cycles in affected programs:     27005 -> 26816 (-0.70%)

but I was seeing patterns in some register-allocation failures in DEQP
tests that looked like the extra MOVs would increase maximum register
pressure in loops.  Some debug code indicates that that's not the case,
though I'm still a bit confused by that result.
2016-10-21 14:12:22 -07:00
Eric Anholt
a689b8b9df vc4: Add a comment with discussion of how simulation works. 2016-10-21 14:12:22 -07:00
Eric Anholt
83ffb607b7 vc4: Move simulator winsys mapping and tracking to the simulator.
One tiny hack is left in vc4_bufmgr.c for what kind of mapping we got so
that we can free it.
2016-10-21 14:12:22 -07:00
Eric Anholt
1c38ee380d vc4: Move simulator memory management to a u_mm.h heap.
Now we aren't limited to 256MB total allocated across a driver instance,
just 256MB at one time.  We're still copying in and out, which should get
fixed.
2016-10-21 14:12:22 -07:00