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winsys/amdgpu: allocate FMASK properly
I expect no change in behavior, because r600_texture.c forces the same tile mode as the base texture has. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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1 changed files with 4 additions and 2 deletions
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@ -387,7 +387,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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/* Set the micro tile type. */
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if (flags & RADEON_SURF_SCANOUT)
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AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
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else if (flags & RADEON_SURF_Z_OR_SBUFFER)
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else if (flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
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AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
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else
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AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
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@ -395,6 +395,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
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AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
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AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
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AddrSurfInfoIn.flags.fmask = (flags & RADEON_SURF_FMASK) != 0;
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AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
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AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
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AddrSurfInfoIn.flags.tcCompatible = (flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
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@ -402,7 +403,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
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/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
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* requested, because TC-compatible HTILE requires 2D tiling.
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*/
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AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible;
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AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
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!(flags & RADEON_SURF_FMASK);
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/* DCC notes:
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* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
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