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gallium/radeon: make r600_gfx_write_fence more generic

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-03 15:32:36 +02:00
parent edf56fb428
commit 462e3cdf3b
4 changed files with 34 additions and 14 deletions
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35
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -80,10 +80,27 @@ void radeon_shader_binary_clean(struct radeon_shader_binary *b)
* pipe_context
*/
void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
uint64_t va, uint32_t old_value, uint32_t new_value)
/**
* Write an EOP event.
*
* \param event EVENT_TYPE_*
* \param event_flags Optional cache flush flags (TC)
* \param data_sel 1 = fence, 3 = timestamp
* \param buf Buffer
* \param va GPU address
* \param old_value Previous fence value (for a bug workaround)
* \param new_value Fence value to write for this event.
*/
void r600_gfx_write_event_eop(struct r600_common_context *ctx,
unsigned event, unsigned event_flags,
unsigned data_sel,
struct r600_resource *buf, uint64_t va,
uint32_t old_fence, uint32_t new_fence)
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
unsigned op = EVENT_TYPE(event) |
EVENT_INDEX(5) |
event_flags;
if (ctx->chip_class == CIK) {
/* Two EOP events are required to make all engines go idle
@ -91,20 +108,18 @@ void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource
* is written.
*/
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, old_value); /* immediate data */
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
radeon_emit(cs, old_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
EVENT_INDEX(5));
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(1));
radeon_emit(cs, new_value); /* immediate data */
radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel));
radeon_emit(cs, new_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);

7
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -705,8 +705,11 @@ r600_invalidate_resource(struct pipe_context *ctx,
struct pipe_resource *resource);
/* r600_common_pipe.c */
void r600_gfx_write_fence(struct r600_common_context *ctx, struct r600_resource *buf,
uint64_t va, uint32_t old_value, uint32_t new_value);
void r600_gfx_write_event_eop(struct r600_common_context *ctx,
unsigned event, unsigned event_flags,
unsigned data_sel,
struct r600_resource *buf, uint64_t va,
uint32_t old_fence, uint32_t new_fence);
unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
void r600_gfx_wait_fence(struct r600_common_context *ctx,
uint64_t va, uint32_t ref, uint32_t mask);

3
src/gallium/drivers/radeon/r600_query.c
View file

@ -671,7 +671,8 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
RADEON_PRIO_QUERY);
if (fence_va)
r600_gfx_write_fence(ctx, query->buffer.buf, fence_va, 0, 0x80000000);
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
query->buffer.buf, fence_va, 0, 0x80000000);
}
static void r600_query_hw_emit_stop(struct r600_common_context *ctx,

3
src/gallium/drivers/radeonsi/si_perfcounter.c
View file

@ -590,7 +590,8 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
{
struct radeon_winsys_cs *cs = ctx->gfx.cs;
r600_gfx_write_fence(ctx, buffer, va, 1, 0);
r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, 1,
buffer, va, 1, 0);
r600_gfx_wait_fence(ctx, va, 0, 0xffffffff);
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));