Commit graph

162653 commits

Author SHA1 Message Date
Karol Herbst
eae281e788 rusticl/kernel: use binding for filling image channel data and order
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
b44bf80ee6 rusticl: use texture vars for readonly images
This is needed by zink

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
10144c1f0b rusticl: do not DCE any samplers or textures
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
f8dd64739e radeonsi: do not DCE texture vars
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
761a2819b5 nir: properly handle CL textures
Without this tex operations would reference images as the texture, which
doesn't really makes much sense. So move to a model closer to Vulkan by
using discrete texture and sampler variables instead.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
915403ea6c nir/gather_info: take texture vars into account when counting textures
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
829d6487c0 glsl: add texture subpass variants
Dzn needs those as it lowers images to textures and we want to be more
consistent about texture ops using texture vars instead of images.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Karol Herbst
87526f79db glsl: fix buffer texture type
Fixes: 3ace6b968b ("compiler/types: Add a texture type")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>
2022-11-10 10:21:34 +00:00
Samuel Pitoiset
d2563e6600 ac/nir: do not convert GS outputs to the expected variable size on GFX11
Outputs are always considered 32-bits.
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19612>
2022-11-10 07:30:08 +00:00
Yonggang Luo
26a6d16db0 zink: Only #include <vulkan/vulkan_core.h> instead #include <vulkan/vulkan.h> in kopper_interface.h
It's pulled too much system dependent headers before this commit
when #include <vulkan/vulkan.h> directly,

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>
2022-11-10 06:59:42 +00:00
Yonggang Luo
5425e05f2f zink: struct kopper_surface is not accessed, remove it in kopper_interface.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>
2022-11-10 06:59:42 +00:00
Yonggang Luo
4c409b921b zink: Indent with 3 space in zink/zink_kopper.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>
2022-11-10 06:59:42 +00:00
Yonggang Luo
4b337638bb wgl: Trim trailing spaces in stw_st.c
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>
2022-11-10 06:59:42 +00:00
Yonggang Luo
0b82281e3e util: Use include_directories('..') instead include_directories('.') for inc_util
So include util headers are always using util/ prefix in mesa code base
And prevent including files under src/util without util/ prefix

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19546>
2022-11-10 06:27:25 +00:00
Yonggang Luo
e399dc3544 util: normalize include files under src/util/*.h with util/ prefix in mesa code base
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19546>
2022-11-10 06:27:25 +00:00
Yonggang Luo
beea3548ce util: Move texcompress template files into util/format
Because these files are accessed in  util/format/u_format_*.c
To make sure util are self contained we need move these files

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19547>
2022-11-10 05:35:41 +00:00
Yonggang Luo
0c12a39682 mesa: include <util/*.h> instead macros.h in texcompress_bptc_tmp.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19547>
2022-11-10 05:35:41 +00:00
Yonggang Luo
f6ed016fe9 util: Replace the usage of ALIGN16 with alignas(16) and them remove ALIGN16 macro
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19565>
2022-11-10 05:04:12 +00:00
Yonggang Luo
956935abaf vulkan: Replace _Alignas with alignas
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19565>
2022-11-10 05:04:12 +00:00
Yonggang Luo
38b2402b5f meson: Use deps_for_libmesa_util for idep_mesautil instead hand crafted list
Now the idep_mesautilc11 have no need reference when idep_mesautil is referenced

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19526>
2022-11-10 11:57:22 +08:00
Yonggang Luo
4d1a293e73 meson: Indent util/meson.build with 2 space
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19526>
2022-11-10 11:57:19 +08:00
Alyssa Rosenzweig
35a531fcd4 agx: Don't assert on texop twice
This is already asserted for lod modes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
ededb108d9 agx: Implement unary math ops
Implement nir_op_bitfield_reverse, nir_op_bit_count, and
nir_op_ufind_msb. These map to native instructions.  With appropriate
integer render target and multiple render target support, passes:

   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findLSB.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findLSB.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findMSB.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findMSB.*fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
44ccdca768 agx: Implement {i,u}mul_2x32_64
With support for MRT in the driver (not included here), passes:

   dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.int_highp_fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.int_highp_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
74a884f73c agx: Implement nir_op_unpack_64_2x32_split_{x,y}
Used in the umul_extended lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
ea88ebefb9 agx/ra: Remove index_to_reg
Use stronger asserts instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
dea00bcc8f agx: Add CSE optimization pass
Ported from the Bifrost compiler, in turn based on the ir3 one. This
cleans up a lot of junk we emit during NIR->AGX and will help with some
SSA RA troubles.

total instructions in shared programs: 34803 -> 34381 (-1.21%)
instructions in affected programs: 18652 -> 18230 (-2.26%)
helped: 198
HURT: 0
helped stats (abs) min: 1.0 max: 28.0 x̄: 2.13 x̃: 1
helped stats (rel) min: 0.31% max: 12.50% x̄: 3.94% x̃: 2.78%
95% mean confidence interval for instructions value: -2.45 -1.81
95% mean confidence interval for instructions %-change: -4.40% -3.48%
Instructions are helped.

total bytes in shared programs: 238094 -> 234824 (-1.37%)
bytes in affected programs: 126472 -> 123202 (-2.59%)
helped: 200
HURT: 0
helped stats (abs) min: 6.0 max: 168.0 x̄: 16.35 x̃: 8
helped stats (rel) min: 0.37% max: 17.65% x̄: 4.25% x̃: 3.38%
95% mean confidence interval for bytes value: -18.49 -14.21
95% mean confidence interval for bytes %-change: -4.67% -3.84%
Bytes are helped.

total halfregs in shared programs: 10078 -> 10107 (0.29%)
halfregs in affected programs: 565 -> 594 (5.13%)
helped: 22
HURT: 22
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.23 x̃: 1
helped stats (rel) min: 5.71% max: 25.00% x̄: 23.38% x̃: 25.00%
HURT stats (abs)   min: 2.0 max: 4.0 x̄: 2.55 x̃: 2
HURT stats (rel)   min: 4.44% max: 30.77% x̄: 15.61% x̃: 12.73%
95% mean confidence interval for halfregs value: 0.03 1.28
95% mean confidence interval for halfregs %-change: -10.17% 2.40%
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
4387d0886d agx: Describe whether instructions may be reordered
As per NIR, for the benefit of CSE. It is assumed that instructions that
cannot be eliminated also cannot be reordered.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
27869f6966 agx: Add and use replace_src helper
From Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
adf3cbc04c agx: Use nir_opt_phi_precision
No shader-db changes, but helped a custom shader I wrote to test loops.
My shader-db is too small.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
98f0ebf264 agx: Pass agx_index to agx_copy
More straightforward interface and will allow including immediates later
if we want to.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
023f27fada agx: Coalesce collects when possible
Track collects and use them as affinities when choosing registers. On
glmark2:

total instructions in shared programs: 5498 -> 5388 (-2.00%)
instructions in affected programs: 2748 -> 2638 (-4.00%)
helped: 31
HURT: 0
helped stats (abs) min: 1.0 max: 12.0 x̄: 3.55 x̃: 3
helped stats (rel) min: 0.09% max: 57.14% x̄: 10.58% x̃: 5.97%
95% mean confidence interval for instructions value: -4.61 -2.49
95% mean confidence interval for instructions %-change: -15.16% -6.00%
Instructions are helped.

total bytes in shared programs: 37280 -> 36620 (-1.77%)
bytes in affected programs: 18880 -> 18220 (-3.50%)
helped: 31
HURT: 0
helped stats (abs) min: 6.0 max: 72.0 x̄: 21.29 x̃: 18
helped stats (rel) min: 0.07% max: 48.98% x̄: 9.16% x̃: 5.17%
95% mean confidence interval for bytes value: -27.64 -14.94
95% mean confidence interval for bytes %-change: -13.03% -5.29%
Bytes are helped.

total halfregs in shared programs: 1267 -> 1279 (0.95%)
halfregs in affected programs: 37 -> 49 (32.43%)
helped: 0
HURT: 9
HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.33 x̃: 1
HURT stats (rel)   min: 16.67% max: 66.67% x̄: 35.58% x̃: 28.57%
95% mean confidence interval for halfregs value: 0.95 1.72
95% mean confidence interval for halfregs %-change: 21.50% 49.67%
Halfregs are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
4cc2427ad6 agx: Introduce agx_foreach_ssa_{src,dest} macros
These are convenient iterators especially in the register allocator.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
4971870441 agx/ra: Factor out assign_regs
Prepare to record bookkeeping needed for live range splits.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
2b806b5cf8 agx/ra: Use BITSET_*_RANGE in some places
A bit neater.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
be5357a353 agx: Free dests of splits that are never read
Otherwise the registers "leak", bloating register pressure by
arbitrarily large amounts. This is easy to handle in DCE by rewriting to
a null destination, though we could use a sideband channel if we didn't
want null destinations in the IR.

glmark2 subset of shader-db is much improved:

total instructions in shared programs: 7324 -> 7313 (-0.15%)
instructions in affected programs: 483 -> 472 (-2.28%)
helped: 5
HURT: 2

total bytes in shared programs: 42788 -> 42722 (-0.15%)
bytes in affected programs: 2808 -> 2742 (-2.35%)
helped: 5
HURT: 2

total halfregs in shared programs: 2421 -> 2058 (-14.99%)
halfregs in affected programs: 1235 -> 872 (-29.39%)
helped: 28
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
9a48c35668 agx: Refuse to handle discontiguous iter
This will cause problems with register allocation.

instructions HURT:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 135 -> 136 (0.74%)
instructions HURT:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 84 -> 85 (1.19%)

bytes HURT:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 914 -> 922 (0.88%)
bytes HURT:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 574 -> 580 (1.05%)

halfregs helped:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 20 -> 19 (-5.00%)
halfregs helped:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 25 -> 23 (-8.00%)
halfregs helped:   shaders/glmark/7-3.shader_test MESA_SHADER_FRAGMENT: 11 -> 10 (-9.09%)
halfregs helped:   shaders/glmark/4-2.shader_test MESA_SHADER_FRAGMENT: 23 -> 19 (-17.39%)

total instructions in shared programs: 5716 -> 5718 (0.03%)
instructions in affected programs: 219 -> 221 (0.91%)
helped: 0
HURT: 2

total bytes in shared programs: 38118 -> 38132 (0.04%)
bytes in affected programs: 1488 -> 1502 (0.94%)
helped: 0
HURT: 2

total halfregs in shared programs: 1639 -> 1631 (-0.49%)
halfregs in affected programs: 79 -> 71 (-10.13%)
helped: 4
HURT: 0
helped stats (abs) min: 1.0 max: 4.0 x̄: 2.00 x̃: 1
helped stats (rel) min: 5.00% max: 17.39% x̄: 9.87% x̃: 8.55%
95% mean confidence interval for halfregs value: -4.25 0.25
95% mean confidence interval for halfregs %-change: -18.31% -1.43%
Inconclusive result (value mean confidence interval includes 0).

Total CPU time (seconds): 11.41 -> 11.72 (2.72%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Alyssa Rosenzweig
af2137883c agx: Don't emit writeout 0xC200
Metal omits this in OpenGL mode, and since we have no clue what it does,
I see no reason for us not to do the same.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
2022-11-10 02:25:09 +00:00
Timothy Arceri
e295ee778b mesa: fix typo from adding glGetObjectLabelEXT
Fixes: 	675bcbb7a1 ("mesa: add EXT_debug_label support")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19607>
2022-11-10 01:07:45 +00:00
Eric Engestrom
069bdef621 docs: update calendar for 22.3.0-rc2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19631>
2022-11-10 01:01:51 +00:00
Emma Anholt
74bbeb5116 ci/iris: Add some flakes from the new testing on JSL.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19628>
2022-11-09 22:07:10 +00:00
Ian Romanick
351b8c6aec intel/fs: Enable nir_op_imul_32x16 and nir_op_umul_32x16 on pre-Gfx7
Even though Intel's CI doesn't test these old platforms anymore, the
validation added in "intel/eu/validate: Validate integer multiplication
source size restrictions" combined with full shader-db runs gives me
confidence in the changes.

Sandy Bridge
total instructions in shared programs: 13902341 -> 13902167 (<.01%)
instructions in affected programs: 30771 -> 30597 (-0.57%)
helped: 66 / HURT: 0

total cycles in shared programs: 741795500 -> 741791931 (<.01%)
cycles in affected programs: 987602 -> 984033 (-0.36%)
helped: 28 / HURT: 5

Iron Lake
total instructions in shared programs: 8365806 -> 8365754 (<.01%)
instructions in affected programs: 1766 -> 1714 (-2.94%)
helped: 10 / HURT: 0

total cycles in shared programs: 248542694 -> 248542378 (<.01%)
cycles in affected programs: 29836 -> 29520 (-1.06%)
helped: 9 / HURT: 0

GM45
total instructions in shared programs: 5187127 -> 5187101 (<.01%)
instructions in affected programs: 891 -> 865 (-2.92%)
helped: 5 / HURT: 0

total cycles in shared programs: 163643914 -> 163643750 (<.01%)
cycles in affected programs: 22206 -> 22042 (-0.74%)
helped: 5 / HURT: 0

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>
2022-11-09 21:34:26 +00:00
Ian Romanick
293ad13e3f intel/fs: Slightly restructure emitting nir_op_imul_32x16 and nir_op_umul_32x16
There are no immediate values at this point, so all of this code was
bunk. :face_palm:

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>
2022-11-09 21:34:26 +00:00
Ian Romanick
ee2a299661 intel/eu/validate: Validate integer multiplication source size restrictions
v2: Expect correct result on BDW in test_eu.

v3: Fix SNB type-size check. Noticed by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>
2022-11-09 21:34:26 +00:00
Ian Romanick
d668512f88 intel/compiler: Fix signed integer range analysis of imax and imin
Some review feedback of an earlier commit caused me to rearrange some
code quite a bit. I wasn't paying enough attention while applying the
later commits, and these breaks should have been returns. As it is, the
result of the imin or imax analysis is overwritten by the default case
handling... effectively the original commit does nothing. :(

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 19914090 -> 19904772 (-0.05%)
instructions in affected programs: 121258 -> 111940 (-7.68%)
helped: 445 / HURT: 0

total cycles in shared programs: 855291535 -> 855266659 (<.01%)
cycles in affected programs: 2737005 -> 2712129 (-0.91%)
helped: 426 / HURT: 17

LOST:   0
GAINED: 3

Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs: 842395356 -> 842338259 (<.01%)
cycles in affected programs: 5460985 -> 5403888 (-1.05%)
helped: 458 / HURT: 0

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 16710449 -> 16708449 (-0.01%)
instructions in affected programs: 44101 -> 42101 (-4.54%)
helped: 75 / HURT: 0

total cycles in shared programs: 882760230 -> 882727923 (<.01%)
cycles in affected programs: 2867797 -> 2835490 (-1.13%)
helped: 62 / HURT: 10

No shader-db change on any other Intel platform.

No fossil-db changes on any Intel platform.

Fixes: 5ec75ca10d ("intel/compiler: Teach signed integer range analysis about imax and imin")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>
2022-11-09 21:34:26 +00:00
Dave Airlie
0f81d9bc88 drm-shim/nouveau: fix the shim to work with nvif ioctl.
The new nouveau code asks the kernel for supported class,
this needs the new nvif interface, so stub it up using
the old code.

unfortunately this also needs a clang warning turned off
so the gnu extension this code needs is enabled in meson

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>
2022-11-09 21:21:22 +00:00
Ben Skeggs
3a94b3b2a7 gv100/ir: noop OP_BAR for now
Let's get stuff rolling and deal with figuring this out later.

Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>
2022-11-09 21:21:22 +00:00
Ben Skeggs
f650c2b076 nvc0: fix ga10x compute launch
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>
2022-11-09 21:21:22 +00:00
Ben Skeggs
56dbf443a8 nvc0: no tex cb mthd on ga10x
I somewhat expect this isn't necessary on Volta and newer too, as the
index is coded into shaders now, but, HW doesn't complain, so leave it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>
2022-11-09 21:21:22 +00:00
Ben Skeggs
25d4db0600 nvc0: recognise ga10x chipsets
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>
2022-11-09 21:21:22 +00:00