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agx: Free dests of splits that are never read

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Otherwise the registers "leak", bloating register pressure by
arbitrarily large amounts. This is easy to handle in DCE by rewriting to
a null destination, though we could use a sideband channel if we didn't
want null destinations in the IR.

glmark2 subset of shader-db is much improved:

total instructions in shared programs: 7324 -> 7313 (-0.15%)
instructions in affected programs: 483 -> 472 (-2.28%)
helped: 5
HURT: 2

total bytes in shared programs: 42788 -> 42722 (-0.15%)
bytes in affected programs: 2808 -> 2742 (-2.35%)
helped: 5
HURT: 2

total halfregs in shared programs: 2421 -> 2058 (-14.99%)
halfregs in affected programs: 1235 -> 872 (-29.39%)
helped: 28
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
This commit is contained in:
Alyssa Rosenzweig 2022-09-21 23:40:14 -04:00 • committed by Marge Bot
parent 9a48c35668
commit be5357a353
1 changed files with 11 additions and 4 deletions
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15
src/asahi/compiler/agx_dce.c
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@ -47,10 +47,17 @@ agx_dce(agx_context *ctx)
bool needed = false;
agx_foreach_dest(I, d) {
if (I->dest[d].type == AGX_INDEX_NORMAL)
needed |= BITSET_TEST(seen, I->dest[d].value);
else if (I->dest[d].type != AGX_INDEX_NULL)
needed = true;
/* Eliminate destinations that are never read, as RA needs to
* handle them specially. Visible only for instructions that write
* multiple destinations (splits) or that write a destination but
* cannot be DCE'd (atomics).
*/
if ((I->dest[d].type == AGX_INDEX_NORMAL) &&
!BITSET_TEST(seen, I->dest[d].value))
I->dest[d] = agx_null();
/* If the destination is actually needed, the instruction is too */
needed |= (I->dest[d].type != AGX_INDEX_NULL);
}
if (!needed) {