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Author SHA1 Message Date
Ian Romanick
e7480f94c1 intel/brw: Combine constants for src0 of integer multiply too 
The majority of cases that would have been affected by this actually
had both sources as integer constants. The earlier commit "intel/rt:
Don't directly generate umul_32x16" allowed those to be constant
folded.

v2: Move the a*-1 block to be near the existing a*-1 block.

No shader-db changes on any Intel platform.

fossil-db results:

All Intel platforms had similar results. (Ice Lake shown)
Totals:
Instrs: 165510246 -> 165510222 (-0.00%)
Cycles: 15125198238 -> 15125195835 (-0.00%); split: -0.00%, +0.00%

Totals from 46 (0.01% of 656118) affected shaders:
Instrs: 36010 -> 35986 (-0.07%)
Cycles: 2613658 -> 2611255 (-0.09%); split: -0.17%, +0.07%

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
 2024-03-12 21:31:30 +00:00
Ian Romanick
dd3bed1d92 intel/brw: Integer multiply w/ DW and W sources is not commutative 
The DW source must be first on all platforms since Gfx7. On previous
platforms it's the other way around.

Unsurprisingly, no shader-db or fossil-db changes. This change is
necessary for the next commit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
 2024-03-12 21:31:30 +00:00
Ian Romanick
93478c095e intel/compiler: Enforce 64-bit RepCtrl restriction in eu_validate 
For some reason, this wasn't always caught in fs_visitor::validate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
 2024-03-12 21:31:30 +00:00
Ian Romanick
31f640bc5f intel/brw: Correctly dump subnr for FIXED_GRF in INTEL_DEBUG=optimizer 
v2: Also update printing FIXED_GRF as destionation. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
 2024-03-12 21:31:30 +00:00
Ian Romanick
f89d9cc53d intel/brw: Silence "statement may fall through" warning 
src/intel/compiler/brw_lower_logical_sends.cpp: In member function ‘bool fs_visitor::lower_logical_sends()’:
src/intel/compiler/brw_lower_logical_sends.cpp:3170:10: warning: this statement may fall through [-Wimplicit-fallthrough=]
 3170 |          if (devinfo->has_lsc) {
      |          ^~
src/intel/compiler/brw_lower_logical_sends.cpp:3174:7: note: here
 3174 |       case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
      |       ^~~~

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27552>
 2024-03-12 21:31:30 +00:00
Alyssa Rosenzweig
a6123a80da nir/opt_shrink_vectors: shrink some intrinsics from start 
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.

v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.

RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)

AGX:

total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)

total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)

total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)

total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)

total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
 2024-03-12 18:17:17 +00:00
Lionel Landwerlin
75c6ad9907 intel/fs: fixup sampler header message 
If you look at the sampler message header on Gfx9+, you'll see that we
mostly only use 2 dwords (dw2 & dw3). DW2 has a bunch of sampler
parameters, DW3 is the sampler handle.

On Gfx9 we can micro optimize by copying r0 into the header because
the HW mostly doesn't care about other DWs. We just have to clear dw2
on non VS/FS stages.

On Gfx11+, we always have to do a careful copy of the r0.3 bits to
mask out the bottom unrelated bits. So there, just clearing the entire
header makes more sense.

On Xe2+, the dw4 of the header references the sampler feedback surface
handle and bit0 is a boolean to know whether to use that surface or
not. So it *REALLY* matters to have that as 0. If we copy r0, we'll
get random bits in dw4, leading to enable that surface.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28082>
 2024-03-12 07:25:45 +00:00
Caio Oliveira
e1afffe7fa intel/brw: Use hstride instead of stride for accumulator 
The `stride` field is not meant to be used by ARFs (like the
accumulator), and is always 1.  Use the `hstride` instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28064>
 2024-03-09 18:26:24 +00:00
Caio Oliveira
7a038cc097 intel/elk: Clean up unused code in elk_compiler.h 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:19 +00:00
Caio Oliveira
be73fa1434 intel/elk: Remove multi-polygon support 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:19 +00:00
Caio Oliveira
fd3a815a5b intel/elk: Remove remaining Gfx9+ code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:19 +00:00
Caio Oliveira
ea12b38602 intel/elk: Remove uses of intel_device_info_is_9lp() 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
9f5213923e intel/elk: Remove Gfx9+-only passes 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
fb2eee2aaa intel/elk: Remove use_tcs_multi_patch 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
abbb7d64f5 intel/elk: Remove Gfx9+ from NIR auxiliary code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
64ff9fa5ae intel/elk: Remove Gfx9+ from disasm 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
566e3c675e intel/elk: Remove Gfx9+ from asm grammar 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
936528cda5 intel/elk: Remove Gfx9+ from Reg related code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
f170d8395b intel/elk: Remove Gfx9+ from FS generator 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
3d867e2fc7 intel/elk: Remove coarse pixel handling 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
7bce435dca intel/elk: Remove Gfx9+ from EU emission 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
d9e7682ccc intel/elk: Remove Gfx9+ from thread payload 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
241a03b8ec intel/elk: Remove Gfx9+ from passes 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
2b6b786feb intel/elk: Remove FB_WRITE_LOGICAL_SRC_SRC_STENCIL 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
7b651ac6c3 intel/elk: Remove Gfx9+ from compile/run functions 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
cb2d96af6a intel/elk: Remove Gfx9+ from nir conversion 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
6b6de68b1c intel/elk: Remove validation code for Gfx9+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
9f80fc3d70 intel/elk: Remove unused SEND features 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
2b15a90cc3 intel/elk: Remove unused sources from ELK_SHADER_OPCODE_SEND 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
e44bacfa91 intel/elk: Remove Xe2 logical sends lowering 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
ff64e68ef4 intel/elk: Remove ex_desc and ex_mlen from elk_inst 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
75e13ac705 intel/elk: Remove Gfx12.5 URB message 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
a3f67c2d3a intel/elk: Remove FB_READ opcodes 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
77ba6f5dcd intel/elk: Remove Gfx9+ dataport messages 
Note GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ is marked as Gfx9 but
it is in the bspec and the PRM does mention it (although not in the
list), so keep it around since we've been using it for a while now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
59c5c67d22 intel/elk: Rename symbols for A64 OWord Block R/W messages 
These are also present in Gfx8, so use the GFX8 instead of
GFX9 as prefix to avoid confusion.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
05d78994a7 intel/elk: Remove Gfx9+ sampler messages and modes 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
9b709e31cb intel/elk: Remove Gfx12 SFIDs and related LSC code 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
43b2261ab5 intel/elk: Remove SYNC opcode and SWSB annotations 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
37cd18e30e intel/elk: Remove encoding for Gfx9+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
accac95c0d intel/elk: Remove EU compaction logic for Gfx9+ 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:18 +00:00
Caio Oliveira
e8c4104362 intel/elk: Remove IADD3 opcode 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Caio Oliveira
d1049408b5 intel/elk: Remove ROR and ROL opcodes 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Caio Oliveira
28a7265b10 intel/elk: Remove DP4A opcode 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Caio Oliveira
9e58170f84 intel/elk: Remove BTD and RT opcodes 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Caio Oliveira
24569b8079 intel/elk: Remove DPAS opcode 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Caio Oliveira
7b90470ca1 intel/elk: Remove split sends 
They are not supported in Gfx8-.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
 2024-03-07 15:53:17 +00:00
Kenneth Graunke
edf14f4b7c intel/brw: Unindent code after previous change 
I kept things indented in the previous patch to make the diffs easier to
read, but there's no reason to continue doing so.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27959>
 2024-03-05 12:03:31 +00:00
Kenneth Graunke
4c10613625 intel/brw: Remove SIMD lowering to a larger SIMD size 
On Gfx4, we had to emulate SIMD8 texturing with SIMD16 for some message
types.  This ceased to be a thing with Gfx5 and hasn't come up again.

So, we can simply assert that we are truly "SIMD splitting", and assume
that the lowered size is smaller than the original instruction size.
This avoids some mental complexity as we can always think of the split
instructions as taking apart, operating on, and recombining subsets of
the original values.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27959>
 2024-03-05 12:03:31 +00:00
Kenneth Graunke
bb191e3af5 intel/brw: Call constant combining after copy propagation/algebraic 
This copy propagation can create MADs with immediates in src1, which
need to be cleaned up by constant combining (which puts them back in
VGRFs).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876>
 2024-03-05 11:39:26 +00:00
Kenneth Graunke
e8ef184677 intel/brw: Make register coalescing obey the g112-g127 restriction 
opt_register_coalesce can sometimes unpleasantly coalesce both
SENDS payload sources into the larger of the two registers.
This can break the assumption that the VGRFs for sources 2-3
must occupy no more than 16 registers, so they fit in g112-127.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27876>
 2024-03-05 11:39:26 +00:00