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Code Issues Projects Releases Packages Wiki Activity Actions 4

intel/elk: Remove ROR and ROL opcodes

Browse source 
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>
This commit is contained in:
Caio Oliveira 2024-02-09 22:05:23 -08:00 • committed by Marge Bot
parent 28a7265b10
commit d1049408b5
14 changed files with 1 additions and 50 deletions
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2
src/intel/compiler/elk/elk_compiler.c
View file

@ -116,8 +116,6 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->has_bfm = devinfo->ver >= 7;
nir_options->has_bfi = devinfo->ver >= 7;
nir_options->has_rotate16 = devinfo->ver >= 11;
nir_options->has_rotate32 = devinfo->ver >= 11;
nir_options->lower_bitfield_reverse = devinfo->ver < 7;
nir_options->lower_find_lsb = devinfo->ver < 7;
nir_options->lower_ifind_msb = devinfo->ver < 7;

4
src/intel/compiler/elk/elk_eu.c
View file

@ -671,10 +671,6 @@ static const struct elk_opcode_desc opcode_descs[] = {
{ ELK_OPCODE_SMOV, 106, "smov", 0, 0, GFX_GE(GFX12) },
{ ELK_OPCODE_ASR, 12, "asr", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_ASR, 108, "asr", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_ROR, 14, "ror", 2, 1, GFX11 },
{ ELK_OPCODE_ROR, 110, "ror", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_ROL, 15, "rol", 2, 1, GFX11 },
{ ELK_OPCODE_ROL, 111, "rol", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_CMP, 16, "cmp", 2, 1, GFX_LT(GFX12) },
{ ELK_OPCODE_CMP, 112, "cmp", 2, 1, GFX_GE(GFX12) },
{ ELK_OPCODE_CMPN, 17, "cmpn", 2, 1, GFX_LT(GFX12) },

2
src/intel/compiler/elk/elk_eu_emit.c
View file

@ -1052,8 +1052,6 @@ ALU2(SHR)
ALU2(SHL)
ALU1(DIM)
ALU2(ASR)
ALU2(ROL)
ALU2(ROR)
ALU3(CSEL)
ALU1(FRC)
ALU1(RNDD)

2
src/intel/compiler/elk/elk_eu_opcodes.h
View file

@ -26,8 +26,6 @@ enum elk_opcode {
ELK_OPCODE_DIM, /**< Gfx7.5 only */
ELK_OPCODE_SMOV, /**< Gfx8+ */
ELK_OPCODE_ASR,
ELK_OPCODE_ROR, /**< Gfx11+ */
ELK_OPCODE_ROL, /**< Gfx11+ */
ELK_OPCODE_CMP,
ELK_OPCODE_CMPN,
ELK_OPCODE_CSEL, /**< Gfx8+ */

2
src/intel/compiler/elk/elk_fs.cpp
View file

@ -4702,8 +4702,6 @@ get_lowered_simd_width(const elk_fs_visitor *shader, const elk_fs_inst *inst)
case ELK_OPCODE_SHR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_ASR:
case ELK_OPCODE_ROR:
case ELK_OPCODE_ROL:
case ELK_OPCODE_CMPN:
case ELK_OPCODE_CSEL:
case ELK_OPCODE_F32TO16:

2
src/intel/compiler/elk/elk_fs_builder.h
View file

@ -649,8 +649,6 @@ namespace elk {
ALU1(RNDE)
ALU1(RNDU)
ALU1(RNDZ)
ALU2(ROL)
ALU2(ROR)
ALU2(SAD2)
ALU2_ACC(SADA2)
ALU2(SEL)

2
src/intel/compiler/elk/elk_fs_combine_constants.cpp
View file

@ -1411,8 +1411,6 @@ elk_fs_visitor::opt_combine_constants()
case ELK_OPCODE_ASR:
case ELK_OPCODE_BFI1:
case ELK_OPCODE_ROL:
case ELK_OPCODE_ROR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_SHR:
if (inst->src[0].file == IMM) {

2
src/intel/compiler/elk/elk_fs_copy_propagation.cpp
View file

@ -1204,8 +1204,6 @@ try_constant_propagate(const elk_compiler *compiler, elk_fs_inst *inst,
case ELK_OPCODE_BFE:
case ELK_OPCODE_BFI1:
case ELK_OPCODE_BFI2:
case ELK_OPCODE_ROL:
case ELK_OPCODE_ROR:
case ELK_OPCODE_SHL:
case ELK_OPCODE_SHR:
case ELK_OPCODE_OR:

10
src/intel/compiler/elk/elk_fs_generator.cpp
View file

@ -1855,16 +1855,6 @@ elk_fs_generator::generate_code(const elk_cfg_t *cfg, int dispatch_width,
case ELK_OPCODE_SHL:
elk_SHL(p, dst, src[0], src[1]);
break;
case ELK_OPCODE_ROL:
assert(devinfo->ver >= 11);
assert(src[0].type == dst.type);
elk_ROL(p, dst, src[0], src[1]);
break;
case ELK_OPCODE_ROR:
assert(devinfo->ver >= 11);
assert(src[0].type == dst.type);
elk_ROR(p, dst, src[0], src[1]);
break;
case ELK_OPCODE_F32TO16:
elk_F32TO16(p, dst, src[0]);
break;

7
src/intel/compiler/elk/elk_fs_nir.cpp
View file

@ -1848,13 +1848,6 @@ fs_nir_emit_alu(nir_to_elk_state &ntb, nir_alu_instr *instr,
break;
case nir_op_urol:
bld.ROL(result, op[0], op[1]);
break;
case nir_op_uror:
bld.ROR(result, op[0], op[1]);
break;
case nir_op_pack_half_2x16_split:
bld.emit(ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);
break;

10
src/intel/compiler/elk/elk_gram.y
View file

@ -199,12 +199,6 @@ i965_asm_binary_instruction(int opcode,
case ELK_OPCODE_PLN:
elk_PLN(p, dest, src0, src1);
break;
case ELK_OPCODE_ROL:
elk_ROL(p, dest, src0, src1);
break;
case ELK_OPCODE_ROR:
elk_ROR(p, dest, src0, src1);
break;
case ELK_OPCODE_SAD2:
fprintf(stderr, "Opcode ELK_OPCODE_SAD2 unhandled\n");
break;
@ -408,7 +402,7 @@ add_label(struct elk_codegen *p, const char* label_name, enum instr_label_type t
%token <integer> NENOP NOP NOT
%token <integer> OR
%token <integer> PLN POP PUSH
%token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
%token <integer> RET RNDD RNDE RNDU RNDZ
%token <integer> SAD2 SADA2 SEL SHL SHR SMOV SUBB SYNC
%token <integer> SEND SENDC
%token <integer> WAIT WHILE
@ -821,8 +815,6 @@ binaryopcodes:
| MACH
| MUL
| PLN
| ROL
| ROR
| SAD2
| SADA2
| SUBB

2
src/intel/compiler/elk/elk_ir_performance.cpp
View file

@ -322,8 +322,6 @@ namespace {
case ELK_OPCODE_FBL:
case ELK_OPCODE_CBIT:
case ELK_OPCODE_ADDC:
case ELK_OPCODE_ROR:
case ELK_OPCODE_ROL:
case ELK_OPCODE_SUBB:
case ELK_OPCODE_SAD2:
case ELK_OPCODE_SADA2:

2
src/intel/compiler/elk/elk_lex.l
View file

@ -116,8 +116,6 @@ rndd { yylval.integer = ELK_OPCODE_RNDD; return RNDD; }
rnde { yylval.integer = ELK_OPCODE_RNDE; return RNDE; }
rndu { yylval.integer = ELK_OPCODE_RNDU; return RNDU; }
rndz { yylval.integer = ELK_OPCODE_RNDZ; return RNDZ; }
rol { yylval.integer = ELK_OPCODE_ROL; return ROL; }
ror { yylval.integer = ELK_OPCODE_ROR; return ROR; }
sad2 { yylval.integer = ELK_OPCODE_SAD2; return SAD2; }
sada2 { yylval.integer = ELK_OPCODE_SADA2; return SADA2; }
sel { yylval.integer = ELK_OPCODE_SEL; return SEL; }

2
src/intel/compiler/elk/elk_shader.cpp
View file

@ -926,8 +926,6 @@ elk_backend_instruction::can_do_source_mods() const
case ELK_OPCODE_CBIT:
case ELK_OPCODE_FBH:
case ELK_OPCODE_FBL:
case ELK_OPCODE_ROL:
case ELK_OPCODE_ROR:
case ELK_OPCODE_SUBB:
case ELK_SHADER_OPCODE_BROADCAST:
case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: