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intel/brw: Unindent code after previous change
I kept things indented in the previous patch to make the diffs easier to read, but there's no reason to continue doing so. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27959>
This commit is contained in:
Kenneth Graunke
Marge Bot
parent
4c10613625
commit
edf14f4b7c
1 changed files with 81 additions and 83 deletions
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@ -619,96 +619,94 @@ brw_fs_lower_simd_width(fs_visitor &s)
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bld.at(block, inst).exec_all(inst->force_writemask_all)
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.group(inst->exec_size, inst->group / inst->exec_size);
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{
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/* Split the copies in chunks of the execution width of either the
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* original or the lowered instruction, whichever is lower.
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/* Split the copies in chunks of the execution width of either the
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* original or the lowered instruction, whichever is lower.
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*/
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const unsigned n = DIV_ROUND_UP(inst->exec_size, lower_width);
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const unsigned residency_size = inst->has_sampler_residency() ?
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(reg_unit(s.devinfo) * REG_SIZE) : 0;
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const unsigned dst_size =
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(inst->size_written - residency_size) /
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inst->dst.component_size(inst->exec_size);
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assert(!inst->writes_accumulator && !inst->mlen);
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/* Inserting the zip, unzip, and duplicated instructions in all of
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* the right spots is somewhat tricky. All of the unzip and any
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* instructions from the zip which unzip the destination prior to
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* writing need to happen before all of the per-group instructions
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* and the zip instructions need to happen after. In order to sort
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* this all out, we insert the unzip instructions before \p inst,
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* insert the per-group instructions after \p inst (i.e. before
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* inst->next), and insert the zip instructions before the
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* instruction after \p inst. Since we are inserting instructions
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* after \p inst, inst->next is a moving target and we need to save
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* it off here so that we insert the zip instructions in the right
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* place.
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*
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* Since we're inserting split instructions after after_inst, the
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* instructions will end up in the reverse order that we insert them.
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* However, certain render target writes require that the low group
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* instructions come before the high group. From the Ivy Bridge PRM
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* Vol. 4, Pt. 1, Section 3.9.11:
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*
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* "If multiple SIMD8 Dual Source messages are delivered by the
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* pixel shader thread, each SIMD8_DUALSRC_LO message must be
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* issued before the SIMD8_DUALSRC_HI message with the same Slot
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* Group Select setting."
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*
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* And, from Section 3.9.11.1 of the same PRM:
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*
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* "When SIMD32 or SIMD16 PS threads send render target writes
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* with multiple SIMD8 and SIMD16 messages, the following must
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* hold:
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*
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* All the slots (as described above) must have a corresponding
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* render target write irrespective of the slot's validity. A slot
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* is considered valid when at least one sample is enabled. For
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* example, a SIMD16 PS thread must send two SIMD8 render target
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* writes to cover all the slots.
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*
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* PS thread must send SIMD render target write messages with
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* increasing slot numbers. For example, SIMD16 thread has
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* Slot[15:0] and if two SIMD8 render target writes are used, the
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* first SIMD8 render target write must send Slot[7:0] and the
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* next one must send Slot[15:8]."
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*
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* In order to make low group instructions come before high group
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* instructions (this is required for some render target writes), we
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* split from the highest group to lowest.
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*/
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exec_node *const after_inst = inst->next;
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for (int i = n - 1; i >= 0; i--) {
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/* Emit a copy of the original instruction with the lowered width.
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* If the EOT flag was set throw it away except for the last
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* instruction to avoid killing the thread prematurely.
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*/
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const unsigned n = DIV_ROUND_UP(inst->exec_size, lower_width);
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const unsigned residency_size = inst->has_sampler_residency() ?
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(reg_unit(s.devinfo) * REG_SIZE) : 0;
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const unsigned dst_size =
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(inst->size_written - residency_size) /
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inst->dst.component_size(inst->exec_size);
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fs_inst split_inst = *inst;
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split_inst.exec_size = lower_width;
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split_inst.eot = inst->eot && i == int(n - 1);
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assert(!inst->writes_accumulator && !inst->mlen);
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/* Inserting the zip, unzip, and duplicated instructions in all of
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* the right spots is somewhat tricky. All of the unzip and any
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* instructions from the zip which unzip the destination prior to
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* writing need to happen before all of the per-group instructions
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* and the zip instructions need to happen after. In order to sort
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* this all out, we insert the unzip instructions before \p inst,
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* insert the per-group instructions after \p inst (i.e. before
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* inst->next), and insert the zip instructions before the
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* instruction after \p inst. Since we are inserting instructions
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* after \p inst, inst->next is a moving target and we need to save
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* it off here so that we insert the zip instructions in the right
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* place.
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*
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* Since we're inserting split instructions after after_inst, the
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* instructions will end up in the reverse order that we insert them.
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* However, certain render target writes require that the low group
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* instructions come before the high group. From the Ivy Bridge PRM
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* Vol. 4, Pt. 1, Section 3.9.11:
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*
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* "If multiple SIMD8 Dual Source messages are delivered by the
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* pixel shader thread, each SIMD8_DUALSRC_LO message must be
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* issued before the SIMD8_DUALSRC_HI message with the same Slot
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* Group Select setting."
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*
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* And, from Section 3.9.11.1 of the same PRM:
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*
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* "When SIMD32 or SIMD16 PS threads send render target writes
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* with multiple SIMD8 and SIMD16 messages, the following must
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* hold:
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*
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* All the slots (as described above) must have a corresponding
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* render target write irrespective of the slot's validity. A slot
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* is considered valid when at least one sample is enabled. For
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* example, a SIMD16 PS thread must send two SIMD8 render target
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* writes to cover all the slots.
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*
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* PS thread must send SIMD render target write messages with
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* increasing slot numbers. For example, SIMD16 thread has
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* Slot[15:0] and if two SIMD8 render target writes are used, the
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* first SIMD8 render target write must send Slot[7:0] and the
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* next one must send Slot[15:8]."
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*
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* In order to make low group instructions come before high group
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* instructions (this is required for some render target writes), we
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* split from the highest group to lowest.
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/* Select the correct channel enables for the i-th group, then
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* transform the sources and destination and emit the lowered
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* instruction.
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*/
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exec_node *const after_inst = inst->next;
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for (int i = n - 1; i >= 0; i--) {
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/* Emit a copy of the original instruction with the lowered width.
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* If the EOT flag was set throw it away except for the last
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* instruction to avoid killing the thread prematurely.
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*/
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fs_inst split_inst = *inst;
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split_inst.exec_size = lower_width;
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split_inst.eot = inst->eot && i == int(n - 1);
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const fs_builder lbld = ibld.group(lower_width, i);
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/* Select the correct channel enables for the i-th group, then
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* transform the sources and destination and emit the lowered
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* instruction.
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*/
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const fs_builder lbld = ibld.group(lower_width, i);
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for (unsigned j = 0; j < inst->sources; j++)
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split_inst.src[j] = emit_unzip(lbld.at(block, inst), inst, j);
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for (unsigned j = 0; j < inst->sources; j++)
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split_inst.src[j] = emit_unzip(lbld.at(block, inst), inst, j);
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split_inst.dst = emit_zip(lbld.at(block, inst),
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lbld.at(block, after_inst), inst);
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split_inst.size_written =
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split_inst.dst.component_size(lower_width) * dst_size +
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residency_size;
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split_inst.dst = emit_zip(lbld.at(block, inst),
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lbld.at(block, after_inst), inst);
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split_inst.size_written =
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split_inst.dst.component_size(lower_width) * dst_size +
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residency_size;
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lbld.at(block, inst->next).emit(split_inst);
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}
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inst->remove(block);
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progress = true;
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lbld.at(block, inst->next).emit(split_inst);
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}
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inst->remove(block);
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progress = true;
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}
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if (progress)
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