Commit graph

114581 commits

Author SHA1 Message Date
Lionel Landwerlin
e4da8b9c33 mesa/compiler: rework tear down of builtin/types
The issue we're running into when running CTS is that glsl types are
deleted while builtins depending on them are not.

This happens because on one hand we have glsl types ref counted, but
builtins are not. Instead builtins are destroyed when unloading libGL
or explicitly calling glReleaseShaderCompiler().

This change removes almost entirely any dealing with glsl types
ref/unref by letting the builtins deal with it instead. In turn we
introduce a builtin ref count mechanism. Each GL context takes a
reference on the builtins when compiling a shader for the first time.
It releases the reference when the context is destroyed. It can also
explicitly release those when glReleaseShaderCompiler() is called.

Finally we also take a reference on the glsl types when loading libGL
to avoid recreating glsl types too often.

v2: Ensure we take a reference if we don't have one in link step (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110796
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-21 09:44:10 +02:00
Lionel Landwerlin
9f37bc419c compiler: ensure glsl types are not created without a reference
We want to detect invalid refcounting so assert we have at least one
use before creating types.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-21 09:44:10 +02:00
Lionel Landwerlin
8b913bd1ce nir/tests: take reference on glsl types
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-21 09:44:10 +02:00
Lionel Landwerlin
3ade8f0040 glsl/tests: take refs on glsl types
Much like each driver, tests as standalone entities must take
references on the glsl types.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-21 09:44:10 +02:00
Samuel Pitoiset
41d9873459 radv/gfx10: hardcode some depth+stencil formats in the format table
The script doesn't handle them correctly and D16_UNORM_S8_UINT
isn't supported by the hardware, mark it as invalid.

This fixes warning when generating gfx10_format_table.h.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111393
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-21 08:17:40 +02:00
Samuel Pitoiset
1650e747c6 radv/gfx10: tidy up gfx10_format_table.py
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-21 08:17:38 +02:00
Ilia Mirkin
958390a9bf gallium/vl: use compute preference for all multimedia, not just blit
The compute paths in vl are a bit AMD-specific. For example, they (on
nouveau), try to use a BGRX8 image format, which is not supported.
Fixing all this is probably possible, but since the compute paths aren't
in any way better, it's difficult to care.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Fixes: 9364d66cb7 (gallium/auxiliary/vl: Add video compositor compute shader render)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-20 23:51:39 -04:00
Emil Velikov
cca442f3ba docs: update calendar for 19.2.x
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-20 23:14:53 +01:00
Emil Velikov
a3d42ad248 docs: add 19.3.0-devel release notes template
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-20 22:39:25 +01:00
Emil Velikov
e6c0b493d2 mesa: bump version to 19.3.0-devel
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2019-08-20 22:33:49 +01:00
Erico Nunes
71fb721ca5 lima/ppir: use ra_get_best_spill_node to select spill node
ra_get_best_spill_node is what other users of the mesa register
allocator use.
Switching to it now also fixes an infinite loop issue with ppir regalloc
with the ppir control flow patchset, and also provides a small gain over
the previous herusitic on number of spilled nodes testing with
shader-db.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-08-20 21:16:02 +00:00
Eric Anholt
c1dc84e71d tgsi: Remove unused tgsi_check_soa_dependencies().
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
4ebe6b2e72 tgsi: Drop the SSE2 constants setup that's been dead code since 2011.
The SSE2 executor was removed in 4eb3225b38 ("Remove tgsi_sse2.")

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
98c58355d3 tgsi: drop a stale comment
This was fixed in 912ed84f83 ("tgsi: move to using vector for system
values.")

Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
2019-08-20 13:31:13 -07:00
Eric Anholt
553cd82d64 gitlab-ci: Enable the GLES2/3 CTS on softpipe.
The GLES2 CTS takes about 8 minutes of total runtime (at parallel 4 is
~2 minutes in the test stage if runners are free), while GLES3 takes
about 25.  Since the GLES3 run is pretty expensive, just do a cheap
touch test of 1 out of every 10 tests in the test list on MRs, until
we can get the runtime down.

v2: Drop the full run for now until we can bring runtime down or bring
    up a dedicated mesa runner.

Reviewed-by: Eric Engestrom <eric@engestrom.ch> (v1)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com> (v1)
2019-08-20 13:31:13 -07:00
Jose Maria Casanova Crespo
6c904773fe mesa: reverse no_error on compressed_tex_sub_image for TEX_MODE_CURRENT
This fixes the regression introduced on "mesa: refactor
compressed_tex_sub_image function" that started to crash
KHR-GLES2.texture_3d.compressed_texture.negative_compressed_tex_sub_image

Fixes: 7df233d68d ("mesa: refactor compressed_tex_sub_image function")
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-20 20:45:21 +01:00
Adam Jackson
b283919398 glx: Eliminate glx_config::{rgb,float,colorIndex}Mode
These are redundant with glx_config::renderType, let's just use that
consistently.
2019-08-20 14:05:07 -04:00
Adam Jackson
74ca87e4bc glx: Remove unused glx_config::pixmapMode
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:05:03 -04:00
Adam Jackson
35fc7bdf0e glx: convert glx_config_create_list to one big calloc
Simpler, less failure prone, less malloc overhead, what's not to like.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:05:01 -04:00
Adam Jackson
97d58eabcc glx: convert a malloc+memset to calloc
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:04:59 -04:00
Adam Jackson
cabd09c9e7 glx: Fix parameter documentation of glx_config_create_list
'minimum_size' is not, in fact, an argument to this function.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-20 14:04:56 -04:00
Arcady Goldmints-Orlov
3835535537 anv: inline uniforms blocks don't count toward descriptor set limits
In a descriptor set inline uniform blocks don't use up any bindings.
However, the presence of any inline uniform blocks doed require the
use of the descriptor buffer, which takes up one binding.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 16:48:45 +00:00
Daniel Schürmann
df86c5ffb3 nir: add divergence analysis pass.
This pass expects the shader to be in LCSSA form.
The algorithm is based on 'The Simple Divergence Analysis' from
Diogo Sampaio, Rafael De Souza, Sylvain Collange, Fernando Magno Quintão Pereira.
Divergence Analysis. ACM Transactions on Programming Languages and Systems (TOPLAS)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-08-20 17:40:13 +02:00
Rhys Perry
7b07034931 nir/subgroups: Lower clustered reductions with cluster_size >= subgroup_size into reductions
The behavior for reductions with cluster_size >= subgroup_size is implementation defined.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:10 +02:00
Rhys Perry
911a1dfad2 nir/lcssa: allow to create LCSSA phis for loop-invariant booleans
ACO depends on LCSSA phis for divergent booleans to work correctly.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:05 +02:00
Daniel Schürmann
9c40ad49d5 nir/lcssa: Skip loop invariant variables when converting to LCSSA.
Co-authored-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:40:01 +02:00
Rhys Perry
8a6cfaa15a nir: make nir_to_lcssa() a general NIR pass.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-20 17:39:54 +02:00
Daniel Schürmann
204846ad06 nir/lcssa: handle deref instructions properly
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: 414148cdc1 "nir: Support deref instructions in loop_analyze"
2019-08-20 17:39:52 +02:00
Jose Maria Casanova Crespo
7c56a68c8b tgsi_to_nir: only update TGSI properties of the current shader stage
The implementation introduced in "tgsi_to_nir: be careful about not
losing any TGSI properties silently (v2)" updates all the TGSI properties,
but it didn't take into account that the shader_info structure uses a union
to store the different attributes for each shader stage.

Now we only update the attributes if they affect current shader stage,
avoiding to overwrite members of the union that should be overwritten.
This has created hundreds of regressions in v3d.

For example the TGSI_PROPERTY_VS_BLIT_SGPRS_AMD was overwritting the
same position used by TGSI_PROPERY_CS_FIXED_BLOCK_DEPTH.

Fixes: e300365197 ("tgsi_to_nir: be careful about not losing any TGSI properties silently (v2)")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-20 10:30:21 +00:00
Samuel Pitoiset
83a63a5b12 radv/gfx10: do not emit PA_SC_TILE_STEERING_OVERRIDE twice
CLEAR_STATE emits it for us.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-20 12:13:44 +02:00
Samuel Pitoiset
2ca8629fa9 radv: do not emit PKT3_CONTEXT_CONTROL with AMDGPU 3.6.0+
It's emitted by the kernel.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-08-20 12:13:41 +02:00
Gert Wollny
6a09405368 mesa/program: Take ARB_framebuffers_no_attachments into account in wpos correction
If a drawbuffer is an fbo without an attachment then its 'Height' will be zero,
and we have to take its 'DefaultGeometry.Height' into account.

Fixes on softpipe (with the exception of tests that use multisample):
  dEQP-GLES31.functional.fbo.no_attachments.*

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-20 10:04:24 +02:00
Sagar Ghuge
fe0e9db797 iris: Enable non coherent framebuffer fetch on broadwell
v2: Use GEN_GEN in iris_state (Kenneth Graunke)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:58 -07:00
Sagar Ghuge
57ce422e20 iris: Free resource if failed to allocate surface state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:55 -07:00
Sagar Ghuge
02244bc515 iris: Pass isl_surf to fill_surface_state
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:45 -07:00
Sagar Ghuge
638a157e02 iris: Add infrastructure to support non coherent framebuffer fetch
Create separate SURFACE_STATE for render target read in order to support
non coherent framebuffer fetch on broadwell.

Also we need to resolve framebuffer in order to support CCS_D.

v2: Add outputs_read check (Kenneth Graunke)

v3: 1) Import Curro's comment from get_isl_surf
    2) Rename get_isl_surf method
    3) Clean up allocation in case of failure

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:44 -07:00
Sagar Ghuge
61c0637afb iris: Add helper functions to get tile offset
All helper functions are ported from i965 driver.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:43 -07:00
Sagar Ghuge
7e816991cc iris: Add helper function to get isl dim layout
v2: Add missing space (Caio)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:41 -07:00
Sagar Ghuge
58471e20d2 iris: Add render target read entry in binding table
This will be used in next patches for supporting non coherent
framebuffer fetch on Broadwell.

v2: Fix comment (Kenneth Graunke)

v3: 1) Fix a few nits (Caio)
    2) Add comment (Caio)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-20 00:50:31 -07:00
Kai Wasserbäch
1abe87383e build: Bump C++ standard requirement to C++14 to fix FTBFS with LLVM 10
When building Mesa against a recent LLVM 10 with C++11, the build fails
if the AMD common code is built as well due to "std::index_sequence"
being undeclared.

LLVM requires a minimum of C++14.

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-08-20 05:39:19 +00:00
Rob Herring
d0ec5d38f6 panfrost: Add madvise support to BO cache
The kernel now supports madvise ioctl to indicate which BOs can be freed
when there is memory pressure. Mark BOs purgeable when they are in the
BO cache. The BOs must also be munmapped when they are in the cache or
they cannot be purged.

We could optimize avoiding the madvise ioctl on older kernels once the
driver version bump lands, but probably not worth it given the other
driver features also being added.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2019-08-19 19:33:20 -05:00
Rob Herring
c45c2d7960 panfrost: Sync UAPI header from kernel
Sync the panfrost_drm.h UAPI header with the latest from the kernel.
This adds madvise ioctl and GPU feature params.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2019-08-19 19:33:20 -05:00
Pierre-Eric Pelloux-Prayer
0f07d18e48 mesa: add ext_dsa GetMultiTexLevelParameterEXT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:50:08 -04:00
Pierre-Eric Pelloux-Prayer
e8c5dc9c24 mesa: add EXT_dsa glCompressedMultiTex* functions display list support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:50:07 -04:00
Pierre-Eric Pelloux-Prayer
1cb8e12717 mesa: add EXT_dsa glCompressedMultiTex* functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:50:05 -04:00
Pierre-Eric Pelloux-Prayer
a886025ef5 mesa: add EXT_dsa glCompressedTex* functions display list support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:50:03 -04:00
Pierre-Eric Pelloux-Prayer
8c76221886 mesa: add EXT_dsa glCompressedTexture(Sub)Image1D/2D/3D functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:49:57 -04:00
Pierre-Eric Pelloux-Prayer
7df233d68d mesa: refactor compressed_tex_sub_image function
Combine compressed_tex_sub_image, compressed_tex_sub_image_error and
compressed_tex_sub_image_no_error in a single function.

The added "enum tex_mode mode" parameter allows to implement the
DSA / non-DSA variants and their error/no_error combination.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-19 18:49:43 -04:00
Bas Nieuwenhuizen
6c5d983865 radv: Add Renoir support.
Took the freedom to enable dfsm even though I don't have benchmark
results yet, but it seems Raven-like.

Rest is from radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-08-19 22:34:11 +00:00
Marek Olšák
223b3174bd radeonsi/nir: always lower ballot masks as 64-bit, codegen handles it
This fixes KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks.

This solution is better, because the IR isn't dependent on wave32.
2019-08-19 17:23:38 -04:00