Commit graph

219438 commits

Author SHA1 Message Date
Rhys Perry
e43caba5f4 nir/range_analysis: use sparse array for float analysis
This seems to be faster.

ministat (nir_analyze_fp_range):
Difference at 95.0% confidence
        -592900 +/- 2302.24
        -27.6432% +/- 0.0998961%
        (Student's t, pooled s = 2719.05)

ministat (overall):
Difference at 95.0% confidence
        -76.8333 +/- 27.2345
        -0.632558% +/- 0.223407%
        (Student's t, pooled s = 46.867)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40190>
2026-03-05 11:26:25 +00:00
Rhys Perry
aecbb2a903 nir/range_analysis: use function pointers for lookup
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40190>
2026-03-05 11:26:25 +00:00
Rhys Perry
2731c34891 nir/range_analysis: use SSA index for hash table keys
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40190>
2026-03-05 11:26:25 +00:00
Rhys Perry
5e376e3ed2 nir: add nir_fp_analysis_state
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40190>
2026-03-05 11:26:25 +00:00
Rhys Perry
c0079e09ca nir/range_analysis: set deleted key
If (uintptr_t)&deleted_key is small enough, inserting entries into the
hash table might not work correctly.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40190>
2026-03-05 11:26:25 +00:00
Jose Maria Casanova Crespo
f00cde96b7 broadcom/ci: broaden glx-copy-sub-buffer flake entry on RPi5
The samples=2 variant also flakes, matching the RPi4 pattern which
covers all sample counts. Broaden the entry to match all variants.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40200>
2026-03-05 10:59:51 +00:00
Jose Maria Casanova Crespo
3cd8ea5356 v3d: simplify fast TLB blit format check
The previous commit added a v3d_get_rt_format() check to reject
fast TLB blits when the job's RT format differs from the blit
destination. Since each RT format maps to a unique (internal_type,
bpp) pair via get_internal_type_bpp_for_output_format(), the
rt_format equality check is strictly stronger than the previous
internal_type/bpp comparison.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40200>
2026-03-05 10:59:51 +00:00
Jose Maria Casanova Crespo
5454221cfb v3d: reject fast TLB blit when RT formats don't match
v3d_tlb_blit_fast includes the blit onto a pending job that writes
to the source resource. The TLB data is already unpacked according to
the job's RT format, so storing it with a different RT format performs
a channel reinterpretation rather than a raw byte copy, corrupting the
data.

So when copying from RGB10_A2UI to RG16UI with glCopyImageSubData,
the copy_image path remaps both formats to R16G16_UNORM for a raw
32-bit copy. The fast TLB blit found the pending clear job
(RGB10_A2UI, 4 channels: 10-10-10-2) and stored its TLB data as RG16UI
(2 channels: 16-16), writing the unpacked 10-bit R and G channel values
into 16-bit fields instead of preserving the raw packed bits.

Previous internal_type/bpp check was insufficient: both RGB10_A2UI
and RG16UI share internal_type=16UI and the source bpp (64) exceeds
the destination bpp (32), but their channel layouts are different.

Add a check that the job's source surface RT format matches the blit
destination RT format before allowing the fast path.

Fixes: 66de8b4b5c ("v3d: add a faster TLB blit path")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40200>
2026-03-05 10:59:51 +00:00
Erik Faye-Lund
b8024d7723 pan/lib: harmonize default-case handling
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
There's little point in having two unreachable blocks here. Yeah, sure,
in theory we are a little bit safer against forgetting to add a case for
newly introduced enum values here. But the UNREACHABLE macro should
already tell us when we trigger such cases anyway, and the cost here is
really readability.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40115>
2026-03-05 10:36:58 +00:00
Erik Faye-Lund
df363c48e6 pan/lib: kill compiler-warning
The compiler seems to fail to see that all cases are handled here,
producing a warning thinking "val" can be undefined. So let's make
that very obvious, by replacing the _COUNT-case with a default
block.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40115>
2026-03-05 10:36:58 +00:00
Erik Faye-Lund
16bc5bb40f panvk: fixup v7 check
panvk_image.c isn't a per-arch file, so the PAN_ARCH macro doesn't exist
here. We need to do a run-time check here instead.

Fixes: 01ba87a7fc ("panvk: Relax ms2ss afbc disablement")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40220>
2026-03-05 10:01:12 +00:00
Rhys Perry
7de3552f3f radv: don't mask PS epilog spi_shader_col_format with dual source blending
In case the FS only writes one output.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:24 +00:00
Rhys Perry
e21d2ece56 radeonsi: fix dual-source blending with only one output
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:24 +00:00
Rhys Perry
fdb0c9c066 radeonsi: fix PS epilog dual-source blending with only one color output
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:24 +00:00
Rhys Perry
bc66fd6af1 radeonsi: replace dual_src_blend_swizzle flag with dual_src_blend
We're going to be using this before GFX11 in some situations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:24 +00:00
Rhys Perry
b4dc39f632 ac/nir: fix when both dual source outputs are unwritten
When this is the case. we shouldn't hang or crash.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:23 +00:00
Rhys Perry
82420ebc2c aco: fix PS epilog dual-source blending with only one color output
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40005>
2026-03-05 09:38:23 +00:00
Samuel Pitoiset
783c065f3b radv: always fast-clear non-MSAA color image with comp-to-single on GFX10-10.3
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
This should enable fast-clear for color images with the GENERAL layout
on GFX10-10.3. This seems important because DXVK tends to use that
layout more often now.

There are still issues with MSAA images, so it's only enabled for
single-sampled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40145>
2026-03-05 08:34:43 +00:00
Samuel Pitoiset
9de465da81 radv: remove radv_disable_depth_storage drirc
This was only for TW3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40214>
2026-03-05 07:55:27 +00:00
Samuel Pitoiset
74defc5f24 radv: disable STORAGE for depth-only formats
This is actually not needed because nobody is using storage with
depth-only formats and compression doesn't work at all anyways.

PAL and native don't allow this either.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40214>
2026-03-05 07:55:26 +00:00
Ian Romanick
8624da56ee brw: Also check for ADDRESS file in update_for_reads
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Like accumulators and ARF address registers, the virtual address
registers are not tracked in a way the defs analysis can know
about. This could actually be fixed, but that is future work.

Fixes: b110b06447 ("brw: introduce a new register type for the address register")
Suggested-by: Lionel
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40083>
2026-03-05 00:02:51 +00:00
Ian Romanick
366410e913 brw: Use brw_reg_is_arf in update_for_reads
brw_reg::nr encodes both which ARF it is and which instance of that
ARF. In other words, nr for acc0 and acc2 have some bits that say
BRW_ARF_ACCUMULATOR and some bits that say 0 vs 2. The previous test
would only detect acc0.

Fixes: 0d144821f0 ("intel/brw: Add a new def analysis pass")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40083>
2026-03-05 00:02:51 +00:00
Ian Romanick
a548466186 brw: Don't mark_invalid in update_for_reads for non-VGRF destination
This can occur if NULL or an accumulator is an explicit destination.
update_for_reads still needs to process the sources.

v2: Pass a brw_reg to ::mark_invalid, and do the VGRF check in that one
place.

Fixes: 0d144821f0 ("intel/brw: Add a new def analysis pass")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40083>
2026-03-05 00:02:50 +00:00
Jason Macnak
c3ce55ff21 gfxstream: Fix StagingInfo destruction ordering
Encoders contain a reference to the stream so those should be
destructed first.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39330>
2026-03-04 23:45:40 +00:00
Val Packett
7bd096ca51 util/rust: Add memory map access mode detection to descriptor API
Add a method for determining which MESA_MAP_ACCESS_* flag would be
appropriate for a given OwnedDescriptor, based on both access flags and
write seals (since access mode can be RDWR despite the seals!)

This is useful for virtgpu implementations when mapping incoming buffers
from host software into the guest's address space. Previously Rutabaga
relied on basic heuristics like "SHM is always R/O", but with upcoming
extra protocols to be forwarded over virtgpu channels (like PipeWire)
those assumptions no longer hold true.

Signed-off-by: Val Packett <val@packett.cool>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40132>
2026-03-04 23:12:22 +00:00
Christian Gmeiner
651cf906e2 isaspec: Use %g format for float display to ensure round-trip fidelity
Change the TYPE_FLOAT display format from %f to %g with sufficient
significant digits (%.5g for f16, %.9g for f32), so that float
immediates round-trip correctly through disassembly and assembly.

The %f format loses precision for small values: f16 0x0001 (denormal
~5.96e-8) displays as 0.000000, which parses back as 0x0000. The %g
format uses the minimum significant digits per IEEE 754 and strips
trailing zeros, using scientific notation when needed. Whole-number
values use %.1f to keep them unambiguously float (e.g. "1.0").

Update the etnaviv PEST grammar and the freedreno ir3 lexer/parser to
accept the new output formats (scientific notation, stripped zeros).

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40207>
2026-03-04 22:42:27 +00:00
Caio Oliveira
ce1a9fbbc6 spirv: Remove conversions from vtn_nir_alu_op_for_spirv_opcode()
They were already being handled explicitly in vtn_alu, so just handle
them directly for spec constants too -- that has to do special work
for conversions anyway.  Remove the bit-size parameters from the function.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40157>
2026-03-04 22:04:45 +00:00
Caio Oliveira
6affcb43a7 spirv: Fix spec constant to handle Select for non-native floats
There was an assumption that if the instruction had non-native float
as a source, the first source would have such type.  This doesn't
hold for Select, and the code failed in two ways

- The boolean source of Select was being converted to the non-native
  float type.

- The loop that resolves the bit-size for unsized operands would
  trip at `assert(i == 0)` because Select has more than one source.

Re-organize the code to track the types of the sources independently,
and fix both issues above.

Fixes: 90e1b12890 ("spirv: Add bfloat16 support to SpecConstantOp")
Fixes: 51d3c4c889 ("spirv: support float8 spec constant op")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40157>
2026-03-04 22:04:45 +00:00
Caio Oliveira
b0c3b20bff spirv: Pull constant source fixup to the existing loop
Backport-to: 26.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40157>
2026-03-04 22:04:44 +00:00
Caio Oliveira
1c3c987d5c spirv: Refactor ALU opcode translation to take bit sizes
Only used by Convert operations, so just pass 0 from callers that
are not Convert and clarify that in the code.

Backport-to: 26.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40157>
2026-03-04 22:04:44 +00:00
Sagar Ghuge
3a62dc0218 anv: Set max outstanding ray queries to 1024
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Set max outstanding ray queries to 1024. This value can be tuned later
specific to apps.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40182>
2026-03-04 21:45:14 +00:00
Marek Olšák
cc3401665d radeonsi: rename si_shader_gs/vs -> si_shader_gs/vs_legacy
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
f421eecebe radv,radeonsi: PA_SC_BINNER changes for gfx12
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
22f3761579 radv: make radv_postprocess_binary_config more correct and more readable
- don't set fields that don't exist on some generations
- add gfx_level checks for MEM_ORDERED even when it's technically not needed

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
fd6941650c ac: add ac_cu_info::has_fmask, adjust FMASK checks
Some of these should check has_fmask, others should check < GFX11.

v2: move to ac_cu_info

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
4cfe08e583 ac: set the correct number of Z planes for ALLOW_EXPCLEAR
This is an old driver bug that could cause Z corruption on gfx8-11.5.

v2: handle allow_expclear differently

Cc: mesa-stable

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> (v1)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
4548ccaceb radeonsi: don't set any EXPCLEAR state on gfx12+
it's not supported there

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
fae7aef5ca ac: tidy up ac_hw_cache_flags
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
18bcfbe1b3 ac/llvm: encode LLVM cache flags manually
so that ac_hw_cache_flags doesn't have to match LLVM

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Marek Olšák
ed131f6347 ac/gpu_info: handle more VRAM types
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40022>
2026-03-04 21:14:56 +00:00
Lionel Landwerlin
db964068bf anv: add drirc option to workaround missing application barriers on typed/untyped data
Enable it for Horizon Forbidden West (only seems to have untyped data
issue).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14889
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40187>
2026-03-04 20:40:59 +00:00
Lionel Landwerlin
13bf1a4008 anv: add an analysis pass to detect compute shaders clearing data
Applications often miss emitting barriers between a shader
initializing data & another shader writing data in the same location
afterward. This is very common for UAVs (see vkd3d-proton).

Vkd3d-proton does a pretty good job as inserting missing barriers
between UAV clears & writes. But some applications also have similar
issues with custom shaders. Here we introduce an analysis pass that
recognize shaders doing clear/initialization. We'll use that
information in the following commit to insert barriers after those
shaders.

Since Gfx12.5 our HW has become a lot more sensitive to those issues
due to the introduction of an L1 untyped data cache that is not
coherent across the shader units. On Gfx20+, typed data is also L1
cacheable exposing even more issues.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40187>
2026-03-04 20:40:59 +00:00
Lionel Landwerlin
0722f50d7b anv: remove unused bind_map field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 487586fefa ("anv: implement inline parameter promotion from push constants")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40187>
2026-03-04 20:40:58 +00:00
Yiwei Zhang
f85416e79d ci/venus: skip broken drm display tests
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40227>
2026-03-04 20:20:14 +00:00
Georg Lehmann
6a218e346d nir: remove lower_vector_cmp
Use nir_lower_alu_width or nir_lower_alu_to_scalar instead.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00
Georg Lehmann
f628cd0333 r300: use nir_lower_alu_width to lower vector compare
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00
Georg Lehmann
35746f64ea freedreno/ir2: use nir_lower_alu_width to lower vector compare
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00
Georg Lehmann
4a794ddaef lima: use nir_lower_alu_width to lower vector compare
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00
Georg Lehmann
c40e496361 etnaviv: use nir_lower_alu_width to lower vector compare
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00
Georg Lehmann
0a219d8099 bifrost: use nir_lower_alu_width to lower vector comparisons
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40197>
2026-03-04 19:50:28 +00:00