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anv: add drirc option to workaround missing application barriers on typed/untyped data

Browse source 
Enable it for Horizon Forbidden West (only seems to have untyped data
issue).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14889
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40187>
This commit is contained in:
Lionel Landwerlin 2026-03-03 11:02:52 +02:00 • committed by Marge Bot
parent 13bf1a4008
commit db964068bf
5 changed files with 54 additions and 4 deletions
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6
src/intel/vulkan/anv_instance.c
View file

@ -17,6 +17,8 @@ static const driOptionDescription anv_dri_options[] = {
DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS(0)
DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS_WITH_BARRIER(false)
DRI_CONF_ANV_ASSUME_FULL_SUBGROUPS_WITH_SHARED_MEMORY(false)
DRI_CONF_ANV_BARRIER_POST_TYPED_CLEAR_SHADER(false)
DRI_CONF_ANV_BARRIER_POST_UNTYPED_CLEAR_SHADER(false)
DRI_CONF_ANV_DISABLE_FCV(false)
DRI_CONF_ANV_ENABLE_BUFFER_COMP(false)
DRI_CONF_ANV_DISABLE_DRM_AUX_MODIFIERS(false)
@ -240,6 +242,10 @@ anv_init_dri_options(struct anv_instance *instance)
driQueryOptionb(&instance->dri_options, "anv_disable_drm_ccs_modifiers");
instance->binding_table_block_size = util_next_power_of_two(
driQueryOptioni(&instance->dri_options, "intel_binding_table_block_size"));
instance->barrier_post_typed_clear_shader =
driQueryOptionb(&instance->dri_options, "anv_barrier_post_typed_clear_shader");
instance->barrier_post_untyped_clear_shader =
driQueryOptionb(&instance->dri_options, "anv_barrier_post_untyped_clear_shader");
if (instance->vk.app_info.engine_name &&
!strcmp(instance->vk.app_info.engine_name, "DXVK")) {

2
src/intel/vulkan/anv_private.h
View file

@ -1828,6 +1828,8 @@ struct anv_instance {
bool force_sampler_prefetch;
bool force_compute_surface_prefetch;
unsigned binding_table_block_size;
bool barrier_post_typed_clear_shader;
bool barrier_post_untyped_clear_shader;
/* HW workarounds */
bool no_16bit;

36
src/intel/vulkan/genX_cmd_compute.c
View file

@ -477,6 +477,36 @@ fill_inline_params(struct GENX(COMPUTE_WALKER_BODY) *body,
}
}
static inline void
cmd_buffer_post_dispatch_wa(struct anv_cmd_buffer *cmd_buffer)
{
genX(cmd_buffer_post_dispatch_wa)(cmd_buffer);
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
/* Workaround WaW hazards in applications that clear a buffer and start
* writing to it immediately without a barrier between the clear & write
* operations.
*/
if (cmd_buffer->device->physical->instance->barrier_post_typed_clear_shader &&
(comp_state->shader->bind_map.inferred_behavior & ANV_PIPELINE_BEHAVIOR_CLEAR_TYPED)) {
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT,
"clear shader typed L1 flush app wa");
}
if (cmd_buffer->device->physical->instance->barrier_post_untyped_clear_shader &&
(comp_state->shader->bind_map.inferred_behavior & ANV_PIPELINE_BEHAVIOR_CLEAR_UNTYPED)) {
anv_add_pending_pipe_bits(cmd_buffer,
VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT,
"clear shader untyped L1 flush app wa");
}
}
static inline void
emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer,
const struct brw_cs_prog_data *prog_data,
@ -531,11 +561,9 @@ emit_indirect_compute_walker(struct anv_cmd_buffer *cmd_buffer,
indirect_addr.bo, 0),
);
genX(cmd_buffer_post_dispatch_wa)(cmd_buffer);
cmd_buffer_post_dispatch_wa(cmd_buffer);
}
static inline void
emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
struct anv_address indirect_addr,
@ -595,7 +623,7 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer,
#endif
);
genX(cmd_buffer_post_dispatch_wa)(cmd_buffer);
cmd_buffer_post_dispatch_wa(cmd_buffer);
}
#else /* #if GFX_VERx10 >= 125 */

6
src/util/00-mesa-defaults.conf
View file

@ -1124,6 +1124,12 @@ TODO: document the other workarounds.
<application name="Total War: WARHAMMER III" executable="TotalWarhammer3">
<option name="anv_fake_nonlocal_memory" value="true" />
</application>
<application name="Horizon Forbidden West" executable="HorizonForbiddenWest.exe">
<!-- Missing barrier between clear/init shader & write
shader.
-->
<option name="anv_barrier_post_untyped_clear_shader" value="true" />
</application>
<!-- Source2 games seem confused by the CCS-only memory type being
restricted to images, so allow it for buffers. More details on
the issue:

8
src/util/driconf.h
View file

@ -957,6 +957,14 @@
DRI_CONF_OPT_B(anv_disable_link_time_optimization, def, \
"Disable linking of graphics pipeline shaders")
#define DRI_CONF_ANV_BARRIER_POST_UNTYPED_CLEAR_SHADER(def) \
DRI_CONF_OPT_B(anv_barrier_post_untyped_clear_shader, def, \
"Insert pipeline barriers post clearing shader on untyped data")
#define DRI_CONF_ANV_BARRIER_POST_TYPED_CLEAR_SHADER(def) \
DRI_CONF_OPT_B(anv_barrier_post_typed_clear_shader, def, \
"Insert pipeline barriers post clearing shader on typed data")
/**
* \brief HASVK specific configuration options
*/