We stick to a rule in the driver that each field is only set in a
single place in the driver. Therefore when merging instructions, we
should never have any bit set to 1 from both sides.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30684>
Currently we can end up merging 2 prepacked 3DSTATE_CLIP instructions
where 2 different places in the driver fill the MaximumVPIndex.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30684>
lower_driver_param_to_ubo would call ir3_const_state_mut
unconditionally. However, since 850f2aab03 ("ir3, tu: Use a UBO for VS
primitive params on a750+"), it can be called for the binning VS,
causing an assert. This commit makes sure to only call
ir3_const_state_mut when it's really necessary to have mutable access to
the const state.
Fixes: 2c47ad7774 ("ir3: make ir3_const_state less error-prone to use")
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30718>
This commit solves the shortage-problem at the blit-functions by
checking the number of fence-registers after updating the batch.
If too many registers are used,
the batch-entries and relocs for the current blit function are
removed by setting batch->ptr and reloc_count to value before
the blit call and calling drm_intel_gem_bo_clear_relocs.
This truncated batch is flushed,
and the batch is updated again for the current blit function.
Cc: mesa-stable
Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26769>
If there are no uniforms to push, don't emit the AND or invalidate the
shader analysis. This affects only compute shaders.
Not a significant impact since lots of shaders end up pushing
uniforms. Fossil-db numbers (restricted to compute pipelines only) for DG2
```
Totals:
Instrs: 3071016 -> 3070894 (-0.00%)
Cycle count: 8320268863 -> 8320264519 (-0.00%)
Totals from 122 (2.70% of 4520) affected shaders:
Instrs: 10675 -> 10553 (-1.14%)
Cycle count: 2060003 -> 2055659 (-0.21%)
```
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30631>
This keeps the allow_fallback behavior for Lua dependency when freedreno
tools are used, like it used to be. But will disable the fallback
mechanism otherwise.
For Intel, the dependency is optional and the tool that uses is
skipped when Lua is not available, so it is fine we don't use fallback
there.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30693>
Stop hardcoding LLVM version as 12, instead read it from external/llvm-project.
In 81e20472a0
the location of the LLVM_VERSION_MAJOR definition was moved. This patch accounts for that
by extracting the version from the new location if it exists. If the new file is not present,
it falls back to the old location.
Backport-to: 24.2
Tested-by: Antonio Ospite <antonio.ospite@collabora.com>
Tested-by: Alessandro Astone <alessandro.astone@canonical.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30598>
We need to flip trianges from CW to CCW based on the domain origin
specified as dynamic state. Instead of tracking all this on the CPU,
add a scratch register and do the conversion in the MME.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
This effectively splits the two states apart so that we can set them
independently. Inside the macros, we only update states that have
actually changed which should also be a bit more efficient.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
We're always storing it in a scratch register for register pressure
reasons anyway. We may as well just stash it there as a state reg and
we can avoid emitting it all over the place. This reduces each draw
call to nvk_flush_gfx_state() followed by the actual draw, which is now
independenty of any dynamic state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
mme_set_priv_reg() needs the first three registers to send data to/from
FALCON04. If we don't reserve these in the register space, it may stomp
other things. This only really matters pre-Volta where we need to use
privileged registers for conservative rasterization. However, it's a
good idea to reserve the space none the less.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
Instead of the state part of the simulator being baked in, it's now
broken out into a pluggable component that the simulator talks to via a
function pointer interface. This will let us run the simulator without
the full state simulator under the hood.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
out_args->scratch_offset and in_wg_id_x will alias on <gfx9.
To avoid the conversion code reading a garbage WG ID, move the
scratch/ring offset writing to the very end.
Fixes: 1e354172 ("radv,aco: Convert 1D ray launches to 2D")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30707>
A loop that looks like:
loop {
do_work_1();
if (cond) {
break;
} else {
}
do_work_2();
break;
}
We can't pull that break ahead of do_work_1() after hoisting the initial
do_work_1() out of the loop. So bail in this case.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11711
Fixes: 6b4b044739 ("nir/opt_loop: add loop peeling optimization")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30702>
We should use `.zink-turnip-collabora-manual-rules` instead of
`.collabora-turnip-manual-rules`, since the former correctly reacts to
the zink+turnip file changes.
Fixes: 69eac6dd15 ("ci/a618: Add zink-tu-a618-full")
Reported-by: Valentine Burley <valentine.burley@gmail.com>
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30698>
In pratical the only change here is that batch_bo_pool
are captured to error dumps.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
Those are batch buffers that are not allocated from batch_bo_pool,
so they were left out of error capture without the capture-all
parameter.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30676>
Make sure to take new GRF size into consideration and adjust the
indirect offset according to new size so that when we do the indirect
load with address register, we load right values.
This helps pass the following tests:
- dEQP-VK.binding_model.descriptor_buffer.mutable_descriptor.*geom*
- dEQP-VK.ray_query.*geometry_shader.*
Backport-to: 24.2
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30679>
In !25925 I attempted to fix an error spam caused by the disk cache not
creating parent directories of the cache directory when needed,
resulting in failure to create the disk cache. Presumably that is bad
for performance.
Unfortunately I did a really bad job and only fixed the edge case where
the cache dir is given by $MESA_SHADER_CACHE_DIR rather than the general
case. Here I attempt to be more comprehensive.
Fixes#8294
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30160>
ir3_const_state is shared between the binning and non-binning variants.
The non-binning variant is compiled first and sets up ir3_const_state
after which the binning variant is not supposed to modify it anymore. If
it would, things may go haywire since the layout of the constant state
will change after the non-binning variant already finished compiling.
Currently, the ir3_const_state() accessor takes care of the sharing
(i.e., it returns the non-binning const state for the binning variant)
but nothing would be prevent the binning variant from accidentally
modifying the state. This is handled by restraint from its users.
This commit tries to make it more difficult to accidentally modify the
const state by the binning shader by making the following changes:
- ir3_const_state(): the same logic as before but now returns a const
pointer to prevent the binning variant from (accidentally) modifying
the const state.
- ir3_const_state_mut(): returns a non-const pointer but asserts that it
is not called by the binning variant.
As a corollary ir3_get_driver_ubo() also had to be split in two variants
(const and non-const) as it is called with a pointer to one of the
fields of ir3_const_state.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30256>
