mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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nouveau/mme/fermi: Break the state simulator into a pluggable component
This is equivalent to the previous commit, but for Fermi. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30703>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
aabd7941ce
commit
4d2d7d6c15
2 changed files with 151 additions and 133 deletions
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@ -13,31 +13,8 @@
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#include "nv_push_cl902d.h"
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struct mme_fermi_sim {
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uint32_t param_count;
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const uint32_t *params;
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/* Bound memory ranges */
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uint32_t mem_count;
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struct mme_fermi_sim_mem *mems;
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/* SET_MME_MEM_ADDRESS_A/B */
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uint64_t mem_addr;
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/* RAM, accessed by STATE */
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struct {
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uint32_t data[MME_FERMI_DRAM_COUNT];
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/* SET_MME_MEM_RAM_ADDRESS */
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uint32_t addr;
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} ram;
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struct {
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// TODO: check if read_fifo is supported.
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struct {
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uint32_t data[1024];
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uint64_t count;
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} read_fifo;
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} dma;
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const struct mme_sim_state_ops *state_ops;
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void *state_handler;
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struct {
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unsigned mthd:16;
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@ -45,86 +22,15 @@ struct mme_fermi_sim {
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bool has_mthd:1;
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} mthd;
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/* SET_MME_SHADOW_SCRATCH(i) */
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uint32_t scratch[MME_FERMI_SCRATCH_COUNT];
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uint32_t regs[7];
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uint32_t alu_carry;
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uint16_t ip;
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uint16_t next_ip;
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};
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static uint32_t *
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find_mem(struct mme_fermi_sim *sim, uint64_t addr, const char *op_desc)
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{
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for (uint32_t i = 0; i < sim->mem_count; i++) {
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if (addr < sim->mems[i].addr)
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continue;
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uint64_t offset = addr - sim->mems[i].addr;
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if (offset >= sim->mems[i].size)
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continue;
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assert(sim->mems[i].data != NULL);
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return (uint32_t *)((char *)sim->mems[i].data + offset);
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}
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fprintf(stderr, "FAULT in %s at address 0x%"PRIx64"\n", op_desc, addr);
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abort();
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}
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static uint32_t
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read_dmem(struct mme_fermi_sim *sim, uint64_t addr, const char *op_desc)
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{
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uint32_t ram_index = addr / 4;
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if (ram_index < ARRAY_SIZE(sim->ram.data)) {
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return sim->ram.data[ram_index];
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}
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if (addr >= NV9097_SET_MME_SHADOW_SCRATCH(0) && addr < NV9097_CALL_MME_MACRO(0)) {
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return sim->scratch[ram_index - NV9097_SET_MME_SHADOW_SCRATCH(0) / 4];
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}
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fprintf(stderr, "FAULT in %s at DMEM address 0x%"PRIx64"\n (READ)", op_desc, addr);
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abort();
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}
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static void
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write_dmem(struct mme_fermi_sim *sim, uint64_t addr, uint32_t val, const char *op_desc)
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{
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uint32_t ram_index = addr / 4;
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if (ram_index < ARRAY_SIZE(sim->ram.data)) {
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sim->ram.data[ram_index] = val;
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}
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else if (addr >= NV9097_SET_MME_SHADOW_SCRATCH(0) && addr < NV9097_CALL_MME_MACRO(0)) {
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sim->scratch[ram_index - NV9097_SET_MME_SHADOW_SCRATCH(0) / 4] = val;
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} else {
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fprintf(stderr, "FAULT in %s at DMEM address 0x%"PRIx64" (WRITE)\n", op_desc, addr);
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abort();
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}
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}
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static uint64_t
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read_dmem64(struct mme_fermi_sim *sim, uint64_t addr, const char *op_desc)
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{
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return ((uint64_t)read_dmem(sim, addr, op_desc) << 32) | read_dmem(sim, addr + 4, op_desc);
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}
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static uint32_t load_param(struct mme_fermi_sim *sim)
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{
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if (sim->param_count == 0) {
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// TODO: know what happens on hardware here
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return 0;
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}
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uint32_t param = *sim->params;
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sim->params++;
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sim->param_count--;
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return param;
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return sim->state_ops->load(sim->state_handler);
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}
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static uint32_t load_reg(struct mme_fermi_sim *sim, enum mme_fermi_reg reg)
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@ -150,6 +56,11 @@ static int32_t load_imm(const struct mme_fermi_inst *inst)
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return util_mask_sign_extend(inst->imm, 18);
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}
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static uint32_t load_state(struct mme_fermi_sim *sim, uint16_t addr)
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{
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return sim->state_ops->state(sim->state_handler, addr);
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}
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static uint32_t eval_bfe_lsl(uint32_t value, uint32_t src_bit, uint32_t dst_bit, uint8_t size)
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{
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if (dst_bit > 31 || src_bit > 31) {
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@ -216,7 +127,7 @@ static uint32_t eval_op(struct mme_fermi_sim *sim, const struct mme_fermi_inst *
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case MME_FERMI_OP_BFE_LSL_REG:
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return eval_bfe_lsl(y, inst->bitfield.src_bit, x, inst->bitfield.size);
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case MME_FERMI_OP_STATE:
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return read_dmem(sim, (x + load_imm(inst)) * 4, "STATE");
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return load_state(sim, (x + load_imm(inst)) * 4);
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// TODO: reverse MME_FERMI_OP_UNK6
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default:
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unreachable("Unhandled op");
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@ -238,34 +149,7 @@ emit_mthd(struct mme_fermi_sim *sim, uint32_t val)
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if (!sim->mthd.has_mthd)
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return;
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uint16_t mthd = sim->mthd.mthd;
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write_dmem(sim, mthd, val, "EMIT");
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switch (mthd) {
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case NV9097_SET_REPORT_SEMAPHORE_D: {
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assert(val == 0x10000000);
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uint64_t addr = read_dmem64(sim, NV9097_SET_REPORT_SEMAPHORE_A, "SET_REPORT_SEMAPHORE");
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uint32_t data = read_dmem(sim, NV9097_SET_REPORT_SEMAPHORE_C, "SET_REPORT_SEMAPHORE");
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uint32_t *mem = find_mem(sim, addr, "SET_REPORT_SEMAPHORE");
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*mem = data;
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break;
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}
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case NV902D_SET_MME_DATA_RAM_ADDRESS:
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sim->ram.addr = val;
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break;
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case NV902D_SET_MME_MEM_ADDRESS_B:
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sim->mem_addr = read_dmem64(sim, NV902D_SET_MME_MEM_ADDRESS_A, "SET_MME_MEM_ADDRESS");
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break;
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case NV902D_MME_DMA_READ_FIFOED:
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sim->dma.read_fifo.count = val;
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break;
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default:
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break;
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}
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sim->state_ops->mthd(sim->state_handler, sim->mthd.mthd, val);
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sim->mthd.mthd += sim->mthd.inc * 4;
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}
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@ -323,15 +207,14 @@ eval_inst(struct mme_fermi_sim *sim, const struct mme_fermi_inst *inst)
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}
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}
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void mme_fermi_sim(uint32_t inst_count, const struct mme_fermi_inst *insts,
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uint32_t param_count, const uint32_t *params,
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uint32_t mem_count, struct mme_fermi_sim_mem *mems)
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void
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mme_fermi_sim_core(uint32_t inst_count, const struct mme_fermi_inst *insts,
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const struct mme_sim_state_ops *state_ops,
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void *state_handler)
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{
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struct mme_fermi_sim sim = {
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.param_count = param_count,
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.params = params,
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.mem_count = mem_count,
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.mems = mems,
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.state_ops = state_ops,
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.state_handler = state_handler,
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};
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sim.ip = 0;
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@ -373,3 +256,132 @@ void mme_fermi_sim(uint32_t inst_count, const struct mme_fermi_inst *insts,
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assert(sim.ip < inst_count);
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eval_inst(&sim, &insts[sim.ip]);
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}
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struct mme_fermi_state_sim {
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uint32_t param_count;
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const uint32_t *params;
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/* Bound memory ranges */
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uint32_t mem_count;
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struct mme_fermi_sim_mem *mems;
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/* SET_MME_SHADOW_SCRATCH(i) */
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uint32_t scratch[MME_FERMI_SCRATCH_COUNT];
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struct {
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uint32_t addr_hi;
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uint32_t addr_lo;
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uint32_t data;
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} report_sem;
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};
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static uint32_t *
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find_mem(struct mme_fermi_state_sim *sim, uint64_t addr, const char *op_desc)
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{
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for (uint32_t i = 0; i < sim->mem_count; i++) {
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if (addr < sim->mems[i].addr)
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continue;
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uint64_t offset = addr - sim->mems[i].addr;
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if (offset >= sim->mems[i].size)
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continue;
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assert(sim->mems[i].data != NULL);
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return (uint32_t *)((char *)sim->mems[i].data + offset);
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}
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fprintf(stderr, "FAULT in %s at address 0x%"PRIx64"\n", op_desc, addr);
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abort();
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}
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static uint32_t
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mme_fermi_state_sim_load(void *_sim)
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{
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struct mme_fermi_state_sim *sim = _sim;
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assert(sim->param_count > 0);
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uint32_t data = *sim->params;
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sim->params++;
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sim->param_count--;
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return data;
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}
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static uint32_t
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mme_fermi_state_sim_state(void *_sim, uint16_t addr)
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{
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struct mme_fermi_state_sim *sim = _sim;
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assert(addr % 4 == 0);
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if (NV9097_SET_MME_SHADOW_SCRATCH(0) <= addr &&
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addr < NV9097_CALL_MME_MACRO(0)) {
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uint32_t i = (addr - NV9097_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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return sim->scratch[i];
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}
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return 0;
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}
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static void
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mme_fermi_state_sim_mthd(void *_sim, uint16_t addr, uint32_t data)
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{
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struct mme_fermi_state_sim *sim = _sim;
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assert(addr % 4 == 0);
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switch (addr) {
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case NV9097_SET_REPORT_SEMAPHORE_A:
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sim->report_sem.addr_hi = data;
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break;
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case NV9097_SET_REPORT_SEMAPHORE_B:
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sim->report_sem.addr_lo = data;
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break;
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case NV9097_SET_REPORT_SEMAPHORE_C:
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sim->report_sem.data = data;
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break;
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case NV9097_SET_REPORT_SEMAPHORE_D: {
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assert(data == 0x10000000);
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uint64_t sem_report_addr =
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((uint64_t)sim->report_sem.addr_hi << 32) | sim->report_sem.addr_lo;
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uint32_t *mem = find_mem(sim, sem_report_addr, "SET_REPORT_SEMAPHORE");
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*mem = sim->report_sem.data;
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break;
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}
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default:
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if (NV9097_SET_MME_SHADOW_SCRATCH(0) <= addr &&
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addr < NV9097_CALL_MME_MACRO(0)) {
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uint32_t i = (addr - NV9097_SET_MME_SHADOW_SCRATCH(0)) / 4;
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assert(i <= ARRAY_SIZE(sim->scratch));
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sim->scratch[i] = data;
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} else {
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fprintf(stdout, "%s:\n", P_PARSE_NV9097_MTHD(addr));
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P_DUMP_NV9097_MTHD_DATA(stdout, addr, data, " ");
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}
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break;
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}
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}
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static const struct mme_sim_state_ops mme_fermi_state_sim_ops = {
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.load = mme_fermi_state_sim_load,
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.state = mme_fermi_state_sim_state,
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.mthd = mme_fermi_state_sim_mthd,
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};
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void
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mme_fermi_sim(uint32_t inst_count, const struct mme_fermi_inst *insts,
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uint32_t param_count, const uint32_t *params,
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uint32_t mem_count, struct mme_fermi_sim_mem *mems)
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{
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const uint32_t zero = 0;
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struct mme_fermi_state_sim state_sim = {
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/* We need at least one param because the first param is always
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* preloaded into $r1.
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*/
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.param_count = MAX2(1, param_count),
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.params = param_count == 0 ? &zero : params,
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.mem_count = mem_count,
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.mems = mems,
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};
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mme_fermi_sim_core(inst_count, insts, &mme_fermi_state_sim_ops, &state_sim);
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}
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@ -5,6 +5,8 @@
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#ifndef MME_FERMI_SIM_H
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#define MME_FERMI_SIM_H
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#include "mme_sim.h"
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#include <stdint.h>
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#include <stdlib.h>
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@ -20,6 +22,10 @@ struct mme_fermi_sim_mem {
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size_t size;
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};
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void mme_fermi_sim_core(uint32_t inst_count, const struct mme_fermi_inst *insts,
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const struct mme_sim_state_ops *state_ops,
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void *state_handler);
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void mme_fermi_sim(uint32_t inst_count, const struct mme_fermi_inst *insts,
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uint32_t param_count, const uint32_t *params,
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uint32_t mem_count, struct mme_fermi_sim_mem *mems);
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