13 commits

Author	SHA1	Message	Date
Lionel Landwerlin	1f6cca0800	intel: fixup a few debugging option checks ... Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: ad328bc58d ("intel: Switch uint64_t intel_debug to a bitset") Reviewed-by: Michael Cheng <michael.cheng@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34667>	2025-04-23 18:47:42 +00:00
Kenneth Graunke	be8ec31e72	intel: Move devinfo->has_negative_rhw_bug into the elk compiler ... This is only needed for original 965G/GM clipper code, which only exists in the legacy compiler. Send it off to live with the elk. Reviewed-by: Dylan Baker <dylan.c.baker@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>	2025-03-10 17:23:07 -07:00
Marek Olšák	7f4e36ff7d	gallium: replace PIPE_SHADER_CAP_INDIRECT_INPUT/OUTPUT_ADDR with NIR options ... This is a prerequisite for enabling nir_opt_varyings for all gallium drivers. nir_lower_io_passes (called by the GLSL linker) only uses NIR options to lower indirect IO access before lowering IO and calling nir_opt_varyings. Most drivers report full support for indirect IO and lower it themselves, which prevents compaction of lowered indirectly accessed varyings because nir_opt_varyings doesn't touch indirect varyings. Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> (Rb for asahi) Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com> (for r300) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32423>	2024-12-03 12:57:36 +00:00
Ian Romanick	11c6b6c102	intel/elk: Remove dsign optimization ... This bit from the comment should have been a big red flag: There are currently zero instances of fsign(double(x))*IMM in shader-db or any test suite, so it is hard to care at this time. The implementation of that path was incorrect. The XOR instructions should be predicated like the OR instruction in the non-multiplication path. As a result, dsign(zero_value) * x will not produce the correct result. Instead of fixing this code that is never exercised by anything, replace it with the simple lowering in NIR. Ironically, the vec4 implementation is correct. The odds of encountering an application that is performace limited by dsign performance in vertex processing stages on Ivy Bridge or Haswell is infinitesimal. No shader-db changes on any Intel platform. v2: Delete 's' in emit_fsign as it is now unused. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1] Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>	2024-05-14 01:28:20 +00:00
Caio Oliveira	fd3a815a5b	intel/elk: Remove remaining Gfx9+ code ... Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:19 +00:00
Caio Oliveira	fb2eee2aaa	intel/elk: Remove use_tcs_multi_patch ... Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:18 +00:00
Caio Oliveira	e8c4104362	intel/elk: Remove IADD3 opcode ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:17 +00:00
Caio Oliveira	d1049408b5	intel/elk: Remove ROR and ROL opcodes ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:17 +00:00
Caio Oliveira	28a7265b10	intel/elk: Remove DP4A opcode ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:17 +00:00
Caio Oliveira	24569b8079	intel/elk: Remove DPAS opcode ... Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27629>	2024-03-07 15:53:17 +00:00
Caio Oliveira	c83f92087b	intel/elk: Move nir_options to its own c/h file pair ... This will allow intel-clc tool to use the ELK nir_options in its NIR codepath without having to link with the entire ELK compiler. That way an Anv only build doesn't need to compile ELK. Iris uses that codepath for Gfx8. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>	2024-02-24 00:24:32 +00:00
Caio Oliveira	6648e0ebd3	intel/elk: Rename symbols ... Either replace the BRW prefix with ELK or add an extra ELK prefix. Used the following sed script to perform the renames in this patch: ``` # Simple prefix changes. s/\<BRW_/ELK_/g s/\<brw_/elk_/g s/nir_to_brw/nir_to_elk/g s/\<as_brw_reg\>/as_elk_reg/g s/\<_brw_/_elk_/g # Add prefix to various symbols. # # Initially I've considered using C++ namespaces here, but in various # cases the structs or functions had to be also visible from C code. # So added explicit prefix instead. s/\<backend_instruction/elk_\0/g s/\<backend_reg/elk_\0/g s/\<backend_shader/elk_\0/g s/\<bblock_t\>/elk_\0/g s/\<bblock_link\>/elk_\0/g s/\<cfg_t\>/elk_\0/g s/\<fs_visitor\>/elk_\0/g s/\<fs_reg\>/elk_\0/g s/\<fs_instruction_scheduler\>/elk_\0/g s/\<vec4_instruction_scheduler\>/elk_\0/g s/\<instruction_scheduler\>/elk_\0/g s/\<schedule_node\>/elk_\0/g s/\<schedule_node_child\>/elk_\0/g s/\<\([a-z]*_\)\?thread_payload\>/elk_\1thread_payload/g s/\<fs_generator\>/elk_\0/g s/\<fs_inst\>/elk_\0/g s/\<fs_reg_alloc\>/elk_\0/g s/\<disasm_info\>/elk_\0/g s/\<gfx._math\>/elk_\0/g s/\<gfx7_block_read_scratch\>/elk_\0/g s/\<gfx6_IF\>/elk_\0/g s/\<gfx9_fb_READ\>/elk_\0/g s/\<gfx6_resolve_implied_move\>/elk_\0/g # Opcodes. s/\<opcode op\>/elk_\0/g s/\<opcode mov_op\>/elk_\0/g s/\<opcode opcode\>/elk_\0/g s/enum opcode\>/enum elk_opcode/g s/static opcode\>/static elk_opcode/g s/\<opcode elk_op/elk_opcode elk_op/g s/struct opcode_desc/struct elk_opcode_desc/g s/NUM_BRW_OPCODES/NUM_ELK_OPCODES/g s/\<.._OPCODE_/ELK_\0/g s/\<T.._OPCODE_/ELK_\0/g s/\<VEC4_OPCODE_/ELK_\0/g s/\<VEC4_...\?_OPCODE_/ELK_\0/g s/\<SHADER_OPCODE_/ELK_\0/g # Remaining specific cases. s/\<wm_prog_data_barycentric_modes\>/elk_\0/g s/\<encode_slm_size\>/elk_\0/g s/\<intel_calculate_slm_size\>/elk_\0/g s/\<gfx6_gather_sampler_wa\>/elk_\0/g s/\<is_3src\>/elk_\0/g s/\<WA_/ELK_\0/g s/\<conditional_modifier\>/elk_\0/g s/\<pred_ctrl_align16\>/elk_\0/g s/\<shuffle_from_32bit_read\>/elk_\0/g s/\<shuffle_src_to_dst\>/elk_\0/g s/\<setup_imm_..\?\>/elk_\0/g s/\<opt_predicated_break\>/elk_\0/g s/\<has_bank_conflict\>/elk_\0/g s/\<dead_control_flow_eliminate\>/elk_\0/g s/\<disasm_new_inst_group\>/elk_\0/g s/\<disasm_initialize\>/elk_\0/g s/\<dump_assembly\>/elk_\0/g s/\<disasm_insert_error\>/elk_\0/g s/\<disasm_annotate\>/elk_\0/g s/\<enum lsc_opcode\>/enum elk_lsc_opcode/g s/\<lsc_opcode_/elk_lsc_opcode_/g s/\<lsc_aop_[a-z_]\+\>/elk_\0/g s/\<type_size_vec4\>/elk_\0/g s/\<type_size_dvec4\>/elk_\0/g s/\<type_size_xvec4\>/elk_\0/g s/\<type_size_[a-z4]\+_bytes\>/elk_\0/g s/\<gfx12_systolic_depth\>/elk_\0/g ``` Acked-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>	2024-02-24 00:24:31 +00:00
Caio Oliveira	e6022281f2	intel/elk: Rename files to use elk prefix ... Acked-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>	2024-02-24 00:24:31 +00:00

Renamed from src/intel/compiler/elk/brw_compiler.c (Browse further)