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gallium: replace PIPE_SHADER_CAP_INDIRECT_INPUT/OUTPUT_ADDR with NIR options

Browse source 
This is a prerequisite for enabling nir_opt_varyings for all gallium
drivers.

nir_lower_io_passes (called by the GLSL linker) only uses NIR options
to lower indirect IO access before lowering IO and calling
nir_opt_varyings.

Most drivers report full support for indirect IO and lower it themselves,
which prevents compaction of lowered indirectly accessed varyings because
nir_opt_varyings doesn't touch indirect varyings.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> (Rb for asahi)
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com> (for r300)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32423>
This commit is contained in:
Marek Olšák 2024-11-29 17:43:34 -05:00 • committed by Marge Bot
parent f930201898
commit 7f4e36ff7d
42 changed files with 87 additions and 118 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
docs/gallium/screen.rst
View file

@ -715,10 +715,6 @@ support different features.
* ``PIPE_SHADER_CAP_MAX_TEMPS``: The maximum number of temporary registers.
* ``PIPE_SHADER_CAP_CONT_SUPPORTED``: Whether continue is supported.
* ``PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR``: Whether indirect addressing
of the input file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR``: Whether indirect addressing
of the output file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR``: Whether indirect addressing
of the temporary file is supported.
* ``PIPE_SHADER_CAP_INDIRECT_CONST_ADDR``: Whether indirect addressing

2
src/asahi/compiler/agx_compile.h
View file

@ -369,6 +369,8 @@ static const nir_shader_compiler_options agx_nir_options = {
.lower_int64_options =
(nir_lower_int64_options) ~(nir_lower_iadd64 | nir_lower_imul_2x32_64),
.lower_doubles_options = (nir_lower_doubles_options)(~0),
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.lower_fquantize2f16 = true,
.compact_arrays = true,
.discard_is_demote = true,

2
src/broadcom/compiler/nir_to_vir.c
View file

@ -2768,7 +2768,7 @@ ntq_emit_load_input(struct v3d_compile *c, nir_intrinsic_instr *instr)
{
/* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset).
*
* Right now the driver sets PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR even
* Right now the driver sets support_indirect_inputs even
* if we don't support non-uniform offsets because we also set the
* lower_all_io_to_temps option in the NIR compiler. This ensures that
* any indirect indexing on in/out variables is turned into indirect

3
src/freedreno/ir3/ir3_compiler.c
View file

@ -329,6 +329,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16))
compiler->nir_options.support_16bit_alu = true;
compiler->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
compiler->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
if (!options->disable_cache)
ir3_disk_cache_init(compiler);

2
src/gallium/auxiliary/gallivm/lp_bld_limits.h
View file

@ -118,8 +118,6 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
return LP_MAX_TGSI_TEMPS;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

6
src/gallium/auxiliary/nir/nir_to_tgsi.c
View file

@ -3297,13 +3297,11 @@ ntt_no_indirects_mask(nir_shader *s, struct pipe_screen *screen)
unsigned pipe_stage = pipe_shader_type_from_mesa(s->info.stage);
unsigned indirect_mask = 0;
if (!screen->get_shader_param(screen, pipe_stage,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR)) {
if (!(s->options->support_indirect_inputs & BITFIELD_BIT(pipe_stage))) {
indirect_mask |= nir_var_shader_in;
}
if (!screen->get_shader_param(screen, pipe_stage,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR)) {
if (!(s->options->support_indirect_outputs & BITFIELD_BIT(pipe_stage))) {
indirect_mask |= nir_var_shader_out;
}

2
src/gallium/auxiliary/tgsi/tgsi_exec.h
View file

@ -456,8 +456,6 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
return TGSI_EXEC_NUM_TEMPS;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

2
src/gallium/drivers/asahi/agx_pipe.c
View file

@ -2308,8 +2308,6 @@ agx_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_INTEGERS:

2
src/gallium/drivers/crocus/crocus_screen.c
View file

@ -492,8 +492,6 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
/* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,

2
src/gallium/drivers/d3d12/d3d12_screen.cpp
View file

@ -504,8 +504,6 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEMPS:
return INT_MAX;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
return 0; /* not implemented */

2
src/gallium/drivers/etnaviv/etnaviv_compiler.c
View file

@ -78,6 +78,8 @@ etna_compiler_create(const char *renderer, const struct etna_core_info *info)
.lower_ufind_msb = true,
.has_uclz = true,
.no_integers = info->halti < 2,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};
compiler->regs = etna_ra_setup(compiler);

2
src/gallium/drivers/etnaviv/etnaviv_screen.c
View file

@ -418,8 +418,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
return ubo_enable ? ETNA_MAX_CONST_BUF : 1;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

2
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -705,8 +705,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
return is_ir3(screen) ? 16 : 1;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
/* a2xx compiler doesn't handle indirect: */

4
src/gallium/drivers/i915/i915_screen.c
View file

@ -169,6 +169,8 @@ static const struct nir_shader_compiler_options gallivm_nir_options = {
.lower_vector_cmp = true,
.lower_device_index_to_zero = true,
/* .support_16bit_alu = true, */
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.has_ddx_intrinsics = true,
.no_integers = true,
};
@ -362,8 +364,6 @@ i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:

2
src/gallium/drivers/iris/iris_screen.c
View file

@ -511,8 +511,6 @@ iris_get_shader_param(struct pipe_screen *pscreen,
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
/* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,

2
src/gallium/drivers/lima/lima_program.c
View file

@ -64,6 +64,7 @@ static const nir_shader_compiler_options vs_nir_options = {
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
.no_integers = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.max_varying_expression_cost = 2,
};
@ -87,6 +88,7 @@ static const nir_shader_compiler_options fs_nir_options = {
.force_indirect_unrolling_sampler = true,
.max_unroll_iterations = 32,
.no_integers = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.max_varying_expression_cost = 2,
};

2
src/gallium/drivers/lima/lima_screen.c
View file

@ -271,12 +271,10 @@ get_fragment_shader_param(struct lima_screen *screen,
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* need investigate */
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 0;
default:

2
src/gallium/drivers/llvmpipe/lp_screen.c
View file

@ -672,6 +672,8 @@ static const struct nir_shader_compiler_options gallivm_nir_options = {
.lower_fquantize2f16 = true,
.driver_functions = true,
.scalarize_ddx = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};

4
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -344,8 +344,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 0;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
@ -393,8 +391,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 16;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:

3
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -339,9 +339,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return 65536;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return NV50_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

11
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -410,17 +410,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
return NVC0_MAX_CONSTBUF_SIZE;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return NVC0_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* HW doesn't support indirect addressing of fragment program inputs
* on Volta. The binary driver generates a function to handle every
* possible indirection, and indirectly calls the function to handle
* this instead.
*/
if (class_3d >= GV100_3D_CLASS)
return shader != PIPE_SHADER_FRAGMENT;
return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

5
src/gallium/drivers/panfrost/pan_screen.c
View file

@ -464,11 +464,6 @@ panfrost_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 0;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return dev->arch >= 6;

10
src/gallium/drivers/r300/compiler/nir_to_rc.c
View file

@ -2099,15 +2099,7 @@ static nir_variable_mode
ntr_no_indirects_mask(nir_shader *s, struct pipe_screen *screen)
{
unsigned pipe_stage = pipe_shader_type_from_mesa(s->info.stage);
unsigned indirect_mask = 0;
if (!screen->get_shader_param(screen, pipe_stage, PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR)) {
indirect_mask |= nir_var_shader_in;
}
if (!screen->get_shader_param(screen, pipe_stage, PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR)) {
indirect_mask |= nir_var_shader_out;
}
unsigned indirect_mask = nir_var_shader_in | nir_var_shader_out;
if (!screen->get_shader_param(screen, pipe_stage, PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR)) {
indirect_mask |= nir_var_function_temp;

17
src/gallium/drivers/r300/r300_screen.c
View file

@ -282,8 +282,6 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
return r300screen->caps.num_tex_units;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
@ -369,8 +367,6 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:
@ -538,6 +534,15 @@ static const nir_shader_compiler_options r300_fs_compiler_options = {
.max_unroll_iterations = 64,
};
static const nir_shader_compiler_options gallivm_compiler_options = {
COMMON_NIR_OPTIONS,
.has_fused_comp_and_csel = true,
.max_unroll_iterations = 32,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};
static const void *
r300_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_ir ir,
@ -547,7 +552,9 @@ r300_get_compiler_options(struct pipe_screen *pscreen,
assert(ir == PIPE_SHADER_IR_NIR);
if (r300screen->caps.is_r500) {
if (shader == PIPE_SHADER_VERTEX && !r300screen->caps.has_tcl) {
return &gallivm_compiler_options;
} else if (r300screen->caps.is_r500) {
if (shader == PIPE_SHADER_VERTEX)
return &r500_vs_compiler_options;
else

2
src/gallium/drivers/r600/r600_pipe.c
View file

@ -573,8 +573,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;

2
src/gallium/drivers/r600/r600_pipe_common.c
View file

@ -1438,6 +1438,8 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
rscreen->nir_options_fs = rscreen->nir_options;
rscreen->nir_options_fs.lower_all_io_to_temps = true;
rscreen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
rscreen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
return true;
}

2
src/gallium/drivers/radeonsi/si_get.c
View file

@ -513,8 +513,6 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
return 1;
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:

2
src/gallium/drivers/softpipe/sp_screen.c
View file

@ -94,6 +94,8 @@ static const nir_shader_compiler_options sp_compiler_options = {
* workgroup id.
*/
.lower_cs_local_index_to_id = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};
static const void *

20
src/gallium/drivers/svga/svga_screen.c
View file

@ -479,19 +479,10 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_TEMPS:
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
return MIN2(val, SVGA3D_TEMPREG_MAX);
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/*
* Although PS 3.0 has some addressing abilities it can only represent
* loops that can be statically determined and unrolled. Given we can
* only handle a subset of the cases that the gallium frontend already
* does it is better to defer loop unrolling to the gallium frontend.
*/
return 0;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 0;
@ -549,9 +540,6 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return 0;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
@ -660,8 +648,6 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
return svgascreen->max_const_buffers;
case PIPE_SHADER_CAP_MAX_TEMPS:
return VGPU10_MAX_TEMPS;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return true; /* XXX verify */
@ -722,7 +708,9 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
#define VGPU10_OPTIONS \
.lower_doubles_options = nir_lower_dfloor | nir_lower_dsign | nir_lower_dceil | nir_lower_dtrunc | nir_lower_dround_even, \
.lower_fmod = true, \
.lower_fpow = true
.lower_fpow = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES)
static const nir_shader_compiler_options svga_vgpu9_fragment_compiler_options = {
COMMON_OPTIONS,
@ -738,6 +726,8 @@ static const nir_shader_compiler_options svga_vgpu9_vertex_compiler_options = {
.force_indirect_unrolling = nir_var_function_temp,
.force_indirect_unrolling_sampler = true,
.no_integers = true,
.support_indirect_inputs = BITFIELD_BIT(MESA_SHADER_VERTEX),
.support_indirect_outputs = BITFIELD_BIT(MESA_SHADER_VERTEX),
};
static const nir_shader_compiler_options svga_vgpu10_compiler_options = {

24
src/gallium/drivers/v3d/v3d_screen.c
View file

@ -399,19 +399,6 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type s
return 16;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* We don't currently support this in the backend, but that is
* okay because our NIR compiler sets the option
* lower_all_io_to_temps, which will eliminate indirect
* indexing on all input/output variables by translating it to
* indirect indexing on temporary variables instead, which we
* will then lower to scratch. We prefer this over setting this
* to 0, which would cause if-ladder injection to eliminate
* indirect indexing on inputs.
*/
return 1;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
@ -756,6 +743,17 @@ v3d_screen_get_compiler_options(struct pipe_screen *pscreen,
.has_uclz = true,
.divergence_analysis_options =
nir_divergence_multiple_workgroup_per_compute_subgroup,
/* We don't currently support this in the backend, but that is
* okay because our NIR compiler sets the option
* lower_all_io_to_temps, which will eliminate indirect
* indexing on all input/output variables by translating it to
* indirect indexing on temporary variables instead, which we
* will then lower to scratch. We prefer this over setting this
* to 0, which would cause if-ladder injection to eliminate
* indirect indexing on inputs.
*/
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
/* This will enable loop unrolling in the state tracker so we won't
* be able to selectively disable it in backend if it leads to
* lower thread counts or TMU spills. Choose a conservative maximum to

2
src/gallium/drivers/vc4/vc4_screen.c
View file

@ -277,8 +277,6 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
return 0;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:

18
src/gallium/drivers/virgl/virgl_screen.c
View file

@ -403,16 +403,9 @@ virgl_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
return INT_MAX;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
if ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES) &&
(shader == PIPE_SHADER_VERTEX)) {
return 0;
}
FALLTHROUGH;
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
case PIPE_SHADER_CAP_MAX_INPUTS:
@ -1235,6 +1228,17 @@ virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *c
screen->compiler_options.lower_ldexp = true;
screen->compiler_options.lower_image_offset_to_range_base = true;
screen->compiler_options.lower_atomic_offset_to_range_base = true;
screen->compiler_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
if (screen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR) {
screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_TESS_CTRL) |
BITFIELD_BIT(MESA_SHADER_TESS_EVAL) |
BITFIELD_BIT(MESA_SHADER_GEOMETRY) |
BITFIELD_BIT(MESA_SHADER_FRAGMENT);
if (!(screen->caps.caps.v2.capability_bits & VIRGL_CAP_HOST_IS_GLES))
screen->compiler_options.support_indirect_inputs |= BITFIELD_BIT(MESA_SHADER_VERTEX);
}
slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);

7
src/gallium/drivers/zink/zink_compiler.c
View file

@ -1412,8 +1412,8 @@ zink_screen_init_compiler(struct zink_screen *screen)
.has_isub = true,
.lower_mul_2x32_64 = true,
.support_16bit_alu = true, /* not quite what it sounds like */
.support_indirect_inputs = BITFIELD_MASK(MESA_SHADER_COMPUTE),
.support_indirect_outputs = BITFIELD_MASK(MESA_SHADER_COMPUTE),
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_COMPUTE),
.max_unroll_iterations = 0,
};
@ -1466,6 +1466,9 @@ zink_screen_init_compiler(struct zink_screen *screen)
if (screen->info.have_EXT_shader_demote_to_helper_invocation)
screen->nir_options.discard_is_demote = true;
screen->nir_options.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
screen->nir_options.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES);
}
const void *

2
src/gallium/drivers/zink/zink_screen.c
View file

@ -1237,8 +1237,6 @@ zink_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:

2
src/gallium/include/pipe/p_defines.h
View file

@ -1071,8 +1071,6 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_MAX_TEMPS,
/* boolean caps */
PIPE_SHADER_CAP_CONT_SUPPORTED,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR,
PIPE_SHADER_CAP_INDIRECT_CONST_ADDR,
PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */

2
src/intel/compiler/brw_compiler.c
View file

@ -79,6 +79,8 @@ const struct nir_shader_compiler_options brw_scalar_nir_options = {
.vectorize_tess_levels = true,
.vertex_id_zero_based = true,
.scalarize_ddx = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};
struct brw_compiler *

2
src/intel/compiler/elk/elk_compiler.c
View file

@ -122,6 +122,8 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
nir_options->lower_doubles_options = fp64_options;
nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
nir_options->support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
nir_options->support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
nir_options->force_indirect_unrolling |=
elk_nir_no_indirect_mask(compiler, i);

4
src/intel/compiler/elk/elk_nir_options.c
View file

@ -31,7 +31,9 @@
.vertex_id_zero_based = true, \
.lower_base_vertex = true, \
.support_16bit_alu = true, \
.lower_uniforms_to_ubo = true
.lower_uniforms_to_ubo = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
.support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES)
#define COMMON_SCALAR_OPTIONS \
.lower_to_scalar = true, \

6
src/mesa/state_tracker/st_extensions.c
View file

@ -352,11 +352,9 @@ void st_init_limits(struct pipe_screen *screen,
PIPE_SHADER_CAP_CONT_SUPPORTED);
options->EmitNoIndirectInput =
!screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR);
!(options->NirOptions->support_indirect_inputs & BITFIELD_BIT(sh));
options->EmitNoIndirectOutput =
!screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR);
!(options->NirOptions->support_indirect_outputs & BITFIELD_BIT(sh));
options->EmitNoIndirectTemp =
!screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR);

11
src/nouveau/codegen/nv50_ir_from_nir.cpp
View file

@ -3676,6 +3676,17 @@ nvir_nir_shader_compiler_options(int chipset, uint8_t shader_type)
op.discard_is_demote = true;
op.has_ddx_intrinsics = true;
op.scalarize_ddx = true;
op.support_indirect_inputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_GEOMETRY + 1);
op.support_indirect_outputs = (uint8_t)BITFIELD_MASK(MESA_SHADER_GEOMETRY + 1);
/* HW doesn't support indirect addressing of fragment program inputs
* on Volta. The binary driver generates a function to handle every
* possible indirection, and indirectly calls the function to handle
* this instead.
*/
if (chipset < NVISA_GV100_CHIPSET)
op.support_indirect_outputs |= BITFIELD_BIT(MESA_SHADER_FRAGMENT);
return op;
}

1
src/panfrost/compiler/bifrost_compile.h
View file

@ -100,6 +100,7 @@ void bifrost_compile_shader_nir(nir_shader *nir,
(nir_var_shader_in | nir_var_shader_out | nir_var_function_temp), \
.force_indirect_unrolling_sampler = true, \
.scalarize_ddx = true, \
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES), \
};
DEFINE_OPTIONS(6);

1
src/panfrost/midgard/midgard_compile.h
View file

@ -105,6 +105,7 @@ static const nir_shader_compiler_options midgard_nir_options = {
.force_indirect_unrolling =
(nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
.force_indirect_unrolling_sampler = true,
.support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
};
#endif