intel: Move devinfo->has_negative_rhw_bug into the elk compiler

This is only needed for original 965G/GM clipper code, which only exists
in the legacy compiler.  Send it off to live with the elk.

Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>

src/intel/compiler/elk/elk_clip.h

@@ -94,6 +94,7 @@ struct elk_clip_compile {
    GLuint last_tmp;
 
    bool need_direction;
+   bool has_negative_rhw_bug;
 
    struct intel_vue_map vue_map;
 };

src/intel/compiler/elk/elk_clip_line.c

@@ -143,7 +143,7 @@ static void clip_and_emit_line( struct elk_clip_compile *c )
    elk_clip_init_clipmask(c);
 
    /* -ve rhw workaround */
-   if (p->devinfo->has_negative_rhw_bug) {
+   if (c->has_negative_rhw_bug) {
       elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2),
               elk_imm_ud(1<<20));
       elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
@@ -201,7 +201,7 @@ static void clip_and_emit_line( struct elk_clip_compile *c )
               * Both can be negative on GM965/G965 due to RHW workaround
               * if so, this object should be rejected.
               */
-             if (p->devinfo->has_negative_rhw_bug) {
+             if (c->has_negative_rhw_bug) {
                  elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_LE, c->reg.dp0, elk_imm_f(0.0));
                  elk_IF(p, ELK_EXECUTE_1);
                  {
@@ -227,7 +227,7 @@ static void clip_and_emit_line( struct elk_clip_compile *c )
 
              /* If both are positive, do nothing */
              /* Only on GM965/G965 */
-             if (p->devinfo->has_negative_rhw_bug) {
+             if (c->has_negative_rhw_bug) {
                  elk_CMP(p, vec1(elk_null_reg()), ELK_CONDITIONAL_L, c->reg.dp0, elk_imm_f(0.0));
                  elk_IF(p, ELK_EXECUTE_1);
              }
@@ -243,7 +243,7 @@ static void clip_and_emit_line( struct elk_clip_compile *c )
                                            ELK_PREDICATE_NORMAL);
              }
 
-             if (p->devinfo->has_negative_rhw_bug) {
+             if (c->has_negative_rhw_bug) {
                  elk_ENDIF(p);
              }
          }

src/intel/compiler/elk/elk_clip_tri.c

@@ -628,7 +628,7 @@ void elk_emit_tri_clip( struct elk_clip_compile *c )
 
    /* if -ve rhw workaround bit is set,
       do cliptest */
-   if (p->devinfo->has_negative_rhw_bug) {
+   if (c->has_negative_rhw_bug) {
       elk_AND(p, elk_null_reg(), get_element_ud(c->reg.R0, 2),
               elk_imm_ud(1<<20));
       elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);

src/intel/compiler/elk/elk_compile_clip.c

@@ -42,6 +42,7 @@ elk_compile_clip(const struct elk_compiler *compiler,
    elk_init_codegen(&compiler->isa, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
+   c.has_negative_rhw_bug = compiler->has_negative_rhw_bug;
 
    c.key = *key;
    c.vue_map = *vue_map;

src/intel/compiler/elk/elk_compiler.c

@@ -47,6 +47,8 @@ elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
 
    compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
 
+   compiler->has_negative_rhw_bug = devinfo->verx10 == 40;
+
    /* Default to the sampler since that's what we've done since forever */
    compiler->indirect_ubos_use_sampler = true;
 

src/intel/compiler/elk/elk_compiler.h

@@ -116,6 +116,9 @@ struct elk_compiler {
     */
    bool indirect_ubos_use_sampler;
 
+   /** Whether we have an original 965G/GM clipping bug */
+   bool has_negative_rhw_bug;
+
    /**
     * Calling the ra_allocate function after each register spill can take
     * several minutes. This option speeds up shader compilation by spilling

src/intel/compiler/elk/elk_vec4_visitor.cpp

@@ -834,7 +834,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
    if (devinfo->ver < 6 &&
        ((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
         output_reg[VARYING_SLOT_CLIP_DIST0][0].file != BAD_FILE ||
-        devinfo->has_negative_rhw_bug)) {
+        compiler->has_negative_rhw_bug)) {
       dst_reg header1 = dst_reg(this, glsl_uvec4_type());
       dst_reg header1_w = header1;
       header1_w.writemask = WRITEMASK_W;
@@ -875,7 +875,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
        * Later, clipping will detect ucp[6] and ensure the primitive is
        * clipped against all fixed planes.
        */
-      if (devinfo->has_negative_rhw_bug &&
+      if (compiler->has_negative_rhw_bug &&
           output_reg[ELK_VARYING_SLOT_NDC][0].file != BAD_FILE) {
          src_reg ndc_w = src_reg(output_reg[ELK_VARYING_SLOT_NDC][0]);
          ndc_w.swizzle = ELK_SWIZZLE_WWWW;

src/intel/dev/intel_device_info.c

@@ -111,7 +111,6 @@ static const struct intel_device_info intel_device_info_gfx3 = {
 static const struct intel_device_info intel_device_info_i965 = {
    .ver = 4,
    .platform = INTEL_PLATFORM_I965,
-   .has_negative_rhw_bug = true,
    .num_slices = 1,
    .num_subslices = { 1, },
    .max_eus_per_subslice = 8,

src/intel/dev/intel_device_info.py

@@ -303,8 +303,6 @@ Struct("intel_device_info",
         Member("bool", "has_context_isolation"),
         Member("bool", "has_set_pat_uapi"),
         Member("bool", "has_indirect_unroll"),
-        Member("bool", "has_negative_rhw_bug", compiler_field=True,
-               comment="Intel hardware quirks"),
 
         Member("bool", "has_coarse_pixel_primitive_and_cb", compiler_field=True,
                comment=dedent("""\