Commit graph

19897 commits

Author SHA1 Message Date
Ansari, Muhammad
d42268f3e5 amd/vpelib: Adding new wrapper for register profiling
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[WHY]
To read back register read/write counts from VPEs, we need to add a new
wrapper function.

[HOW]
Added a wrapper that calls build command and populate the register
profiling data structure.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:26 +00:00
Ali, Nawwar
2a5124a09f amd/vpelib: Fix crash during encoding test
[WHY]
Fix crash during encoding test

Co-authored-by: Agate, Jesse <Jesse.Agate+amdeng@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Agate, Jesse
39187b36b5 amd/vpelib: Add RGB 601 Primaires to BG Color
[WHY]
RGB 601 Primaries are missing from vpe_is_limited_cs

[HOW]
Add 601 primaries to the switch statement

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-Off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Rouf, Farhan
edf352a71a amd/vpelib: Embedded Buffer Size for 3DLUT FL
[WHY]
The embedded-buffer usage decision should be based on the stream's 3DLUT
mode rather than a loosely defined tm_enabled boolean.

[HOW]
- Replace cmd_info.tm_enabled with cmd_info.lut3d_type
- Add vpe_get_stream_lut3d_type() helper and use it in cmd info/buffer req
- Prefix internal helpers (vpe_calculate_scaling_ratios, vpe_should_generate_cmd_info)

Signed-Off-by: Farhan Rouf <Farhan.Rouf@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Assadian, Navid
dd7c2f9528 amd/vpelib: Reorder function pointers
[HOW]
- Re-order the function pointer assignments to have the same order as
defined.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-Off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
You, Min-Hsuan
e33bbe7ee7 amd/vpelib: refactor minor change
Make dscl_set_scaler_position be a function pointer

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Singed-off-by: Min-Hsuan You <Min-Hsuan.You@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Chan, Roy
3d750ed881 amd/vpelib: fix uninitialized variable
[WHY]
The packet header has uninitialized fields that can introduce 1b'1 in
reserved bits.

[HOW]
initialize the header to 0

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Roy Chan <Roy.Chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Ali, Nawwar
3216b0c193 amd/vpelib: coding style rectify
Revised the coding style

Co-authored-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:25 +00:00
Ansari, Muhammad
58c544a9bd amd/vpelib: Fix potential overflow calculation
[WHY]
Multiplication result may overflow int before it is converted to long
long

[HOW]
Updated the expression to avoid possible overflow

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Muhammad Ansari <Muhammad.Ansari@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:24 +00:00
Lin, Ricky
dbff0fabf0 amd/vpelib: Augment swizzling modes
[WHY]
Support different generations of swizzle mode.

[HOW]
Added different swizzle mode parameters for supporting plane
description.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Ricky Lin <Ricky.Lin@amdeng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:24 +00:00
Ali, Nawwar
f3db1d5f46 amd/vpelib: update 3dlut and shaper FL
[WHY]
Fast load support is required for 3DLUT and Shaper features.
The calculation logic needs to be modularized and exposed via
the resource interface to support this.

[HOW]
1. Add `calculate_shaper` and `program_fastload` function pointers to the `resource` struct.
2. Move shaper normalization, HDR multiplier update, and 3DLUT update logic from
   `vpe_color_update_movable_cm` into a new core function `vpe_calculate_shaper`.
3. Implement `vpe10_calculate_shaper` and assign it to the resource function table for VPE10 and VPE11.
4. Update `vpe_create_engine` return signature to remove `const` qualifier.

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Nawwar Ali <Nawwar.Ali@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:24 +00:00
Chang, Tomson
4ffd5a1c31 amd/vpelib: avoid using reg_update for multi-thread
[WHY]
Reg_update macro and its lastWritten_value design are static global
variables and cannot support multi-thread usage

[HOW]
remove reg_update usage and combine the separated calls together

Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Tomson Chang <tomson.chang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39848>
2026-02-12 11:56:24 +00:00
Rhys Perry
c811348dc2 radv: include ahit/isec shaders in radv_get_shader_from_executable_index
This is necessary for GetPipelineExecutablePropertiesKHR, RADV_DEBUG and
fossil-db.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39827>
2026-02-12 11:31:37 +00:00
Pierre-Eric Pelloux-Prayer
8f7f7a90b7 radeonsi/sqtt: use pipe_aligned_buffer_create to allocate bo
pipe_aligned_buffer_create can allow allocate 4GB but that's large enough
for now.
PIPE_USAGE_STREAM is used for now to keep the 2 BOs in GTT.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39194>
2026-02-12 10:08:43 +00:00
Samuel Pitoiset
9a6ec08960 radv: enable trimming FS color exports for internal shaders
Some checks are pending
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This should be safe now, and potentially more optimal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
2026-02-12 07:33:58 +00:00
Samuel Pitoiset
dbad9144f2 radv/meta: use R32G32 formats for R64 slow color clears
This is required because CB doesn't support 64-bit formats.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
2026-02-12 07:33:58 +00:00
Samuel Pitoiset
db89f94441 radv/meta: stop trying to reduce the number of format variants
Now that we have a solid logic for caching meta objects, trying to
reduce the number of format variants isn't super useful. In practice,
the shaders would be cached on disk, so this would only allocate few
more bytes for the meta objects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39786>
2026-02-12 07:33:58 +00:00
Samuel Pitoiset
e58ef1b3bc radv: do not set the resume rendering flag for custom resolves
It's not a resume operation, it's a complete new rendering pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:56 +00:00
Samuel Pitoiset
cbf981e99a radv: do not resolve when rendering is suspended
The Vulkan spec says:
    "Store and resolve operations are only performed at the end of a
     render pass instance that does not specify the
     VK_RENDERING_SUSPENDING_BIT_KHR flag."

VK_RENDERING_SUSPENDING_BIT is also illegal with custom resolves.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:56 +00:00
Samuel Pitoiset
c1c031ca91 radv: make sure rendering isn't already active in CmdBeginRendering()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:56 +00:00
Samuel Pitoiset
99344bdfe5 radv: clear rendering state before performing resolves
This is mostly for not calling CmdBeginRendering() while rendering
is already active in order to catch potential driver issues. This
requires a small refactoring of how the rendering info is passed for
resolves though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:55 +00:00
Samuel Pitoiset
4c18a36765 radv: pass VkSampleLocationsInfoEXT for depth/stencil expand
Instead of using an intermediate structure.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:55 +00:00
Samuel Pitoiset
6f279445e7 radv/meta: stop using custom sample locations for color resolves
Only needed for depth/stencil resolves.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39782>
2026-02-12 07:12:54 +00:00
Georg Lehmann
d7814bcad0 aco: remove redundant can_use_DPP declaration
Some checks are pending
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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
2026-02-11 11:34:29 +00:00
Georg Lehmann
fc7b5d7eed aco/opt_postRA: don't optimize across calls
Could do better by checking which registers are clobbered/preserved,
but that's unlikely to be useful anyway.

Backport-to: 26.0

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
2026-02-11 11:34:29 +00:00
Georg Lehmann
10b12a6ee2 aco: handle all SALU that modifies PC in needs_exec_mask
Calls use swappc.

Backport-to: 26.0

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
2026-02-11 11:34:29 +00:00
Georg Lehmann
421a4dacf0 aco/lower_branches: consider jump target of conditional branches based on vcc
Cc: mesa-stable

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39801>
2026-02-11 11:34:29 +00:00
Georg Lehmann
77d05ac1ba aco/optimizer: stop checking precise for med3
No Foz-DB changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
2026-02-10 18:42:03 +00:00
Georg Lehmann
a87cdfc6b7 radv/nir/rt: preserve inf/nan for emulated RT intersect
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
2026-02-10 18:42:02 +00:00
Georg Lehmann
e873b8764a aco/optimizer: use nan preserve flag to prevent incorrect med3
No Foz-DB changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
2026-02-10 18:42:02 +00:00
Samuel Pitoiset
2cd9693a31 radv/meta: remove an useless barrier when fixing up HTILE for copies on compute
The copy operation doesn't use HTILE of the destination image, so the
clear can run in parallel.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:22 +00:00
Samuel Pitoiset
5663ebffc4 radv/meta: skip some HTILE operations when it's decompressed on image stores
Only GFX11-GFX11.5 are affected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:22 +00:00
Samuel Pitoiset
0996b4c527 radv/meta: do not disable compression for depth/stencil expand on compute
This doesn't make sense for the destination image and this would
prevent COMPRESSION_EN=1 to work correctly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:22 +00:00
Samuel Pitoiset
452304897f radv: set COMPRESSION_EN=1 for depth or stencil storage images when supported
On GFX10+, the hardware can write decompressed DWORDS to HTILE when
COMPRESSION_EN=1, which means some HTILE decompression/initialization
operations can be avoided because it automatically mark the tiles that
are touched as uncompressed.

Though according to PAL, there are issues with that on GFX10-10.3, so
it's only enabled on GFX11-11.5.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:22 +00:00
Samuel Pitoiset
6f2b048f84 radv/meta: stop fixing up HTILE after a partial copy
The decompression pass already resets HTILE to its uncompressed state,
so this is just redundant.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:21 +00:00
Samuel Pitoiset
4f41818194 radv/meta: add a function to fixup HTILE metadata for copies on compute queue
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:21 +00:00
Samuel Pitoiset
9f5a20abde radv/meta: fix CmdCopyBufferToImage2() on compute queue with compressed HTILE
Only for partial copies because image stores don't decompress on writes
(ie. HTILE isn't updated by image stores).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39656>
2026-02-10 10:42:21 +00:00
Samuel Pitoiset
17bbd45d59 radv: emit the framebuffer state when rendering begins
Much better.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:02 +00:00
Samuel Pitoiset
e178382fb8 radv: add a new dirty bit for the GFX12 HiZ workaround
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:02 +00:00
Samuel Pitoiset
a010c2694a radv: move {depth,stencil}_compress_disable to the image view extra info
Doesn't have to be a pipeline parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:01 +00:00
Samuel Pitoiset
9abe6d4dc2 radv: remove declared but unused radv_get_dcc_max_uncompressed_block_size()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:01 +00:00
Samuel Pitoiset
8d9fb0744e radv: move color/depth-stencil init surface helpers to radv_image_view.c/h
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:01 +00:00
Samuel Pitoiset
39719c6c44 radv/meta: remove dead code in the gfx depth/stencil clear path
The driver either does a fast-clear using compute or a slow clear
using graphics, so the "fast" clear using graphics isn't used at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
2026-02-09 09:43:00 +00:00
Samuel Pitoiset
e488085942 radv/meta: remove unused saving/restoring rendering state logic
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39729>
2026-02-09 08:41:07 +00:00
Samuel Pitoiset
98186aba36 radv/meta: stop saving/restoring rendering state for color/depth decompressions
These should always happen outside of rendering.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39729>
2026-02-09 08:41:07 +00:00
Samuel Pitoiset
04d5077b00 radv: emit late decompressions for fbfetch slightly earlier
Right after "normal" layout transitions and just before the rendering
state is set, mostly because it doesn't need to be saved/restored
either.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39729>
2026-02-09 08:41:07 +00:00
Samuel Pitoiset
04f6bfae51 radv: only pass custom sample locations when relevant
Custom sample locations are only needed for depth decompression.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39729>
2026-02-09 08:41:07 +00:00
Samuel Pitoiset
ce3539b54f radv: fix late decompressions for fbfetch with more corner cases
With layers, or custom sample locations for depth.
Found this by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39729>
2026-02-09 08:41:06 +00:00
Reilly Brogan
ece5f671b3 amd,compiler: fix const errors found with C23 glibc support
Some checks are pending
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In glibc 2.43 the strstr function now propagate const to the output, triggering -Wincompatible-pointer-types-discards-qualifiers
under clang/gcc with -Werror.

Fix two of these cases by adding the const qualifier.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39767>
2026-02-08 23:18:15 +00:00
Samuel Pitoiset
c817ef30ee radv/meta: remove dead DCC clear code about E5B9B9R9_UFLOAT_PACK32
Some checks are pending
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Only GFX10.3+ supports COLOR_ATTACHMENT/STORAGE with this format, so older
gens can't have DCC either.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39689>
2026-02-06 12:49:36 +00:00