fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 00:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

radv: emit the framebuffer state when rendering begins

Browse source 
Much better.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
This commit is contained in:
Samuel Pitoiset 2026-02-06 10:49:07 +01:00 • committed by Marge Bot
parent e178382fb8
commit 17bbd45d59
2 changed files with 44 additions and 54 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -9624,13 +9624,7 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
primary->shader_upload_seq = MAX2(primary->shader_upload_seq, secondary->shader_upload_seq);
if (!secondary->state.render.has_image_views) {
if (primary->state.render.active && (primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
/* Emit the framebuffer state from primary if secondary
* has been recorded without a framebuffer, otherwise
* fast color/depth clears can't work.
*/
radv_emit_framebuffer_state(primary);
if (primary->state.render.active && (primary->state.dirty & RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE)) {
if (pdev->gfx12_hiz_wa == RADV_GFX12_HIZ_WA_FULL) {
const struct radv_rendering_state *render = &primary->state.render;
const struct radv_image_view *iview = render->ds_att.iview;
@ -10041,10 +10035,10 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
render->gfx12_has_hiz = gfx12_has_hiz;
render->vrs_att = vrs_att;
render->vrs_texel_size = vrs_texel_size;
cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_FRAMEBUFFER | RADV_CMD_DIRTY_BINNING_STATE | RADV_CMD_DIRTY_DEPTH_BIAS_STATE |
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE | RADV_CMD_DIRTY_CB_RENDER_STATE | RADV_CMD_DIRTY_MSAA_STATE |
RADV_CMD_DIRTY_RAST_SAMPLES_STATE | RADV_CMD_DIRTY_PS_STATE | RADV_CMD_DIRTY_PS_EPILOG_SHADER;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_BINNING_STATE | RADV_CMD_DIRTY_DEPTH_BIAS_STATE |
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE | RADV_CMD_DIRTY_CB_RENDER_STATE |
RADV_CMD_DIRTY_MSAA_STATE | RADV_CMD_DIRTY_RAST_SAMPLES_STATE | RADV_CMD_DIRTY_PS_STATE |
RADV_CMD_DIRTY_PS_EPILOG_SHADER;
if (pdev->info.rbplus_allowed)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
@ -10140,6 +10134,8 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
radv_emit_fb_mip_change_flush(cmd_buffer);
radv_emit_framebuffer_state(cmd_buffer);
if (!(pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT))
radv_cmd_buffer_clear_rendering(cmd_buffer, pRenderingInfo);
}
@ -12476,11 +12472,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAGMENT_OUTPUT;
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) {
radv_emit_framebuffer_state(cmd_buffer);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_GUARDBAND) {
radv_emit_guardband_state(cmd_buffer);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_GUARDBAND;

75
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -87,44 +87,43 @@ enum radv_dynamic_state_bits {
enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_PIPELINE = 1ull << 0,
RADV_CMD_DIRTY_INDEX_BUFFER = 1ull << 1,
RADV_CMD_DIRTY_FRAMEBUFFER = 1ull << 2,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 3,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 4,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 5,
RADV_CMD_DIRTY_RBPLUS = 1ull << 6,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 7,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 8,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 9,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 10,
RADV_CMD_DIRTY_FRAGMENT_OUTPUT = 1ull << 11,
RADV_CMD_DIRTY_PS_STATE = 1ull << 12,
RADV_CMD_DIRTY_NGG_STATE = 1ull << 13,
RADV_CMD_DIRTY_TASK_STATE = 1ull << 14,
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE = 1ull << 15,
RADV_CMD_DIRTY_RASTER_STATE = 1ull << 16,
RADV_CMD_DIRTY_MSAA_STATE = 1ull << 17,
RADV_CMD_DIRTY_CLIP_RECTS_STATE = 1ull << 18,
RADV_CMD_DIRTY_TCS_TES_STATE = 1ull << 19,
RADV_CMD_DIRTY_CB_RENDER_STATE = 1ull << 20,
RADV_CMD_DIRTY_VIEWPORT_STATE = 1ull << 21,
RADV_CMD_DIRTY_BINNING_STATE = 1ull << 22,
RADV_CMD_DIRTY_FSR_STATE = 1ull << 23,
RADV_CMD_DIRTY_RAST_SAMPLES_STATE = 1ull << 24,
RADV_CMD_DIRTY_DEPTH_BIAS_STATE = 1ull << 25,
RADV_CMD_DIRTY_VS_PROLOG_STATE = 1ull << 26,
RADV_CMD_DIRTY_BLEND_CONSTANTS_STATE = 1ull << 27,
RADV_CMD_DIRTY_SAMPLE_LOCATIONS_STATE = 1ull << 28,
RADV_CMD_DIRTY_SCISSOR_STATE = 1ull << 29,
RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE = 1ull << 30,
RADV_CMD_DIRTY_LS_HS_CONFIG = 1ull << 31,
RADV_CMD_DIRTY_VGT_PRIM_STATE = 1ull << 32,
RADV_CMD_DIRTY_FORCE_VRS_STATE = 1ull << 33,
RADV_CMD_DIRTY_NGGC_VIEWPORT = 1ull << 34,
RADV_CMD_DIRTY_NGGC_SETTINGS = 1ull << 35,
RADV_CMD_DIRTY_PS_EPILOG_SHADER = 1ull << 36,
RADV_CMD_DIRTY_PS_EPILOG_STATE = 1ull << 37,
RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE = 1ull << 38,
RADV_CMD_DIRTY_ALL = (1ull << 39) - 1,
RADV_CMD_DIRTY_VERTEX_BUFFER = 1ull << 2,
RADV_CMD_DIRTY_STREAMOUT_BUFFER = 1ull << 3,
RADV_CMD_DIRTY_GUARDBAND = 1ull << 4,
RADV_CMD_DIRTY_RBPLUS = 1ull << 5,
RADV_CMD_DIRTY_OCCLUSION_QUERY = 1ull << 6,
RADV_CMD_DIRTY_DB_SHADER_CONTROL = 1ull << 7,
RADV_CMD_DIRTY_STREAMOUT_ENABLE = 1ull << 8,
RADV_CMD_DIRTY_GRAPHICS_SHADERS = 1ull << 9,
RADV_CMD_DIRTY_FRAGMENT_OUTPUT = 1ull << 10,
RADV_CMD_DIRTY_PS_STATE = 1ull << 11,
RADV_CMD_DIRTY_NGG_STATE = 1ull << 12,
RADV_CMD_DIRTY_TASK_STATE = 1ull << 13,
RADV_CMD_DIRTY_DEPTH_STENCIL_STATE = 1ull << 14,
RADV_CMD_DIRTY_RASTER_STATE = 1ull << 15,
RADV_CMD_DIRTY_MSAA_STATE = 1ull << 16,
RADV_CMD_DIRTY_CLIP_RECTS_STATE = 1ull << 17,
RADV_CMD_DIRTY_TCS_TES_STATE = 1ull << 18,
RADV_CMD_DIRTY_CB_RENDER_STATE = 1ull << 19,
RADV_CMD_DIRTY_VIEWPORT_STATE = 1ull << 20,
RADV_CMD_DIRTY_BINNING_STATE = 1ull << 21,
RADV_CMD_DIRTY_FSR_STATE = 1ull << 22,
RADV_CMD_DIRTY_RAST_SAMPLES_STATE = 1ull << 23,
RADV_CMD_DIRTY_DEPTH_BIAS_STATE = 1ull << 24,
RADV_CMD_DIRTY_VS_PROLOG_STATE = 1ull << 25,
RADV_CMD_DIRTY_BLEND_CONSTANTS_STATE = 1ull << 26,
RADV_CMD_DIRTY_SAMPLE_LOCATIONS_STATE = 1ull << 27,
RADV_CMD_DIRTY_SCISSOR_STATE = 1ull << 28,
RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE = 1ull << 29,
RADV_CMD_DIRTY_LS_HS_CONFIG = 1ull << 30,
RADV_CMD_DIRTY_VGT_PRIM_STATE = 1ull << 31,
RADV_CMD_DIRTY_FORCE_VRS_STATE = 1ull << 32,
RADV_CMD_DIRTY_NGGC_VIEWPORT = 1ull << 33,
RADV_CMD_DIRTY_NGGC_SETTINGS = 1ull << 34,
RADV_CMD_DIRTY_PS_EPILOG_SHADER = 1ull << 35,
RADV_CMD_DIRTY_PS_EPILOG_STATE = 1ull << 36,
RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE = 1ull << 37,
RADV_CMD_DIRTY_ALL = (1ull << 38) - 1,
RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE,
};