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radv: move color/depth-stencil init surface helpers to radv_image_view.c/h

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39731>
This commit is contained in:
Samuel Pitoiset 2026-02-09 09:42:55 +01:00 • committed by Marge Bot
parent 39719c6c44
commit 8d9fb0744e
5 changed files with 156 additions and 159 deletions
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1
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -17,6 +17,7 @@
#include "vk_command_buffer.h"
#include "radv_device.h"
#include "radv_image_view.h"
#include "radv_physical_device.h"
#include "radv_pipeline_graphics.h"
#include "radv_video.h"

139
src/amd/vulkan/radv_device.c
View file

@ -1543,13 +1543,6 @@ radv_GetDeviceImageMemoryRequirements(VkDevice device, const VkDeviceImageMemory
radv_DestroyImage(device, image, NULL);
}
static uint32_t
radv_surface_max_layer_count(struct radv_image_view *iview)
{
return iview->vk.view_type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth
: (iview->vk.base_array_layer + iview->vk.layer_count);
}
static unsigned
radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const struct radv_image *image)
{
@ -1565,138 +1558,6 @@ radv_get_dcc_max_uncompressed_block_size(const struct radv_device *device, const
return V_028C78_MAX_BLOCK_SIZE_256B;
}
void
radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
struct radv_image_view *iview)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint64_t va;
const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
const struct radeon_surf *surf = &plane->surface;
memset(cb, 0, sizeof(*cb));
const unsigned num_layers =
iview->image->vk.image_type == VK_IMAGE_TYPE_3D ? (iview->extent.depth - 1) : (iview->image->vk.array_layers - 1);
const struct ac_cb_state cb_state = {
.surf = surf,
.format = radv_format_to_pipe_format(iview->vk.format),
.width = vk_format_get_plane_width(iview->image->vk.format, iview->plane_id, iview->extent.width),
.height = vk_format_get_plane_height(iview->image->vk.format, iview->plane_id, iview->extent.height),
.first_layer = iview->vk.base_array_layer,
.last_layer = radv_surface_max_layer_count(iview) - 1,
.num_layers = num_layers,
.num_samples = iview->image->vk.samples,
.num_storage_samples = iview->image->vk.samples,
.base_level = iview->vk.base_mip_level,
.num_levels = iview->image->vk.mip_levels,
.gfx10 =
{
.nbc_view = iview->nbc_view.valid ? &iview->nbc_view : NULL,
},
};
ac_init_cb_surface(&pdev->info, &cb_state, &cb->ac);
uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
va = iview->image->bindings[plane_id].addr;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = surf,
.cb = &cb->ac,
.va = va,
.base_level = iview->vk.base_mip_level,
.num_samples = iview->image->vk.samples,
.fmask_enabled = radv_image_has_fmask(iview->image),
.cmask_enabled = radv_image_has_cmask(iview->image),
.fast_clear_enabled = !(instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS),
.tc_compat_cmask_enabled = radv_image_is_tc_compat_cmask(iview->image),
.dcc_enabled = radv_dcc_enabled(iview->image, iview->vk.base_mip_level) &&
(pdev->info.gfx_level >= GFX11 || !iview->disable_dcc_mrt),
.gfx10 =
{
.nbc_view = iview->nbc_view.valid ? &iview->nbc_view : NULL,
},
};
ac_set_mutable_cb_surface_fields(&pdev->info, &mutable_cb_state, &cb->ac);
}
void
radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer, struct radv_ds_buffer_info *ds)
{
const struct radeon_surf *surf = &image->planes[0].surface;
assert(image->vk.format == VK_FORMAT_D16_UNORM);
memset(ds, 0, sizeof(*ds));
ds->ac.db_z_info = S_028038_FORMAT(V_028040_Z_16) | S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028038_ZRANGE_PRECISION(1) | S_028038_TILE_SURFACE_ENABLE(1);
ds->ac.db_stencil_info = S_02803C_FORMAT(V_028044_STENCIL_INVALID);
ds->ac.db_depth_size = S_02801C_X_MAX(image->vk.extent.width - 1) | S_02801C_Y_MAX(image->vk.extent.height - 1);
ds->ac.u.gfx6.db_htile_data_base = radv_buffer_get_va(htile_buffer->bo) >> 8;
ds->ac.u.gfx6.db_htile_surface =
S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1) | S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING);
}
void
radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview, VkImageAspectFlags ds_aspects)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
unsigned level = iview->vk.base_mip_level;
bool stencil_only = iview->image->vk.format == VK_FORMAT_S8_UINT;
assert(vk_format_get_plane_count(iview->image->vk.format) == 1);
memset(ds, 0, sizeof(*ds));
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
/* Recommended value for better performance with 4x and 8x. */
ds->db_render_override2 = S_028010_DECOMPRESS_Z_ON_FLUSH(iview->image->vk.samples >= 4) |
S_028010_CENTROID_COMPUTATION_MODE(pdev->info.gfx_level >= GFX10_3);
const struct ac_ds_state ds_state = {
.surf = &iview->image->planes[0].surface,
.va = iview->image->bindings[0].addr,
.format = radv_format_to_pipe_format(iview->image->vk.format),
.width = iview->image->vk.extent.width,
.height = iview->image->vk.extent.height,
.level = level,
.num_levels = iview->image->vk.mip_levels,
.num_samples = iview->image->vk.samples,
.first_layer = iview->vk.base_array_layer,
.last_layer = max_slice,
.stencil_only = stencil_only,
.z_read_only = !(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
.stencil_read_only = !(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
.htile_enabled = radv_htile_enabled(iview->image, level),
.htile_stencil_disabled = radv_image_tile_stencil_disabled(device, iview->image),
.vrs_enabled = radv_image_has_vrs_htile(device, iview->image),
};
ac_init_ds_surface(&pdev->info, &ds_state, &ds->ac);
const struct ac_mutable_ds_state mutable_ds_state = {
.ds = &ds->ac,
.format = radv_format_to_pipe_format(iview->image->vk.format),
.tc_compat_htile_enabled = radv_tc_compat_htile_enabled(iview->image, level),
.zrange_precision = true,
.no_d16_compression = true,
};
ac_set_mutable_ds_surface_fields(&pdev->info, &mutable_ds_state, &ds->ac);
if (pdev->info.gfx_level >= GFX11) {
radv_gfx11_set_db_render_control(device, iview->image->vk.samples, &ds->db_render_control);
}
}
void
radv_gfx11_set_db_render_control(const struct radv_device *device, unsigned num_samples, unsigned *db_render_control)
{

20
src/amd/vulkan/radv_device.h
View file

@ -365,26 +365,6 @@ unsigned radv_get_default_max_sample_dist(int log_samples);
void radv_emit_default_sample_locations(const struct radv_physical_device *pdev, struct radv_cmd_stream *cs,
int nr_samples);
struct radv_color_buffer_info {
struct ac_cb_surface ac;
};
struct radv_ds_buffer_info {
struct ac_ds_surface ac;
uint32_t db_render_override2;
uint32_t db_render_control;
};
void radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
struct radv_image_view *iview);
void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
struct radv_ds_buffer_info *ds);
void radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview, VkImageAspectFlags ds_aspects);
void radv_gfx11_set_db_render_control(const struct radv_device *device, unsigned num_samples,
unsigned *db_render_control);

141
src/amd/vulkan/radv_image_view.c
View file

@ -10,7 +10,9 @@
#include "vk_log.h"
#include "radv_buffer.h"
#include "radv_buffer_view.h"
#include "radv_debug.h"
#include "radv_entrypoints.h"
#include "radv_formats.h"
#include "radv_image.h"
@ -486,6 +488,145 @@ radv_image_view_can_fast_clear(const struct radv_device *device, const struct ra
return true;
}
static uint32_t
radv_surface_max_layer_count(struct radv_image_view *iview)
{
return iview->vk.view_type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth
: (iview->vk.base_array_layer + iview->vk.layer_count);
}
static void
radv_initialise_color_surface(struct radv_device *device, struct radv_color_buffer_info *cb,
struct radv_image_view *iview)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
uint64_t va;
const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
const struct radeon_surf *surf = &plane->surface;
memset(cb, 0, sizeof(*cb));
const unsigned num_layers =
iview->image->vk.image_type == VK_IMAGE_TYPE_3D ? (iview->extent.depth - 1) : (iview->image->vk.array_layers - 1);
const struct ac_cb_state cb_state = {
.surf = surf,
.format = radv_format_to_pipe_format(iview->vk.format),
.width = vk_format_get_plane_width(iview->image->vk.format, iview->plane_id, iview->extent.width),
.height = vk_format_get_plane_height(iview->image->vk.format, iview->plane_id, iview->extent.height),
.first_layer = iview->vk.base_array_layer,
.last_layer = radv_surface_max_layer_count(iview) - 1,
.num_layers = num_layers,
.num_samples = iview->image->vk.samples,
.num_storage_samples = iview->image->vk.samples,
.base_level = iview->vk.base_mip_level,
.num_levels = iview->image->vk.mip_levels,
.gfx10 =
{
.nbc_view = iview->nbc_view.valid ? &iview->nbc_view : NULL,
},
};
ac_init_cb_surface(&pdev->info, &cb_state, &cb->ac);
uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
va = iview->image->bindings[plane_id].addr;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = surf,
.cb = &cb->ac,
.va = va,
.base_level = iview->vk.base_mip_level,
.num_samples = iview->image->vk.samples,
.fmask_enabled = radv_image_has_fmask(iview->image),
.cmask_enabled = radv_image_has_cmask(iview->image),
.fast_clear_enabled = !(instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS),
.tc_compat_cmask_enabled = radv_image_is_tc_compat_cmask(iview->image),
.dcc_enabled = radv_dcc_enabled(iview->image, iview->vk.base_mip_level) &&
(pdev->info.gfx_level >= GFX11 || !iview->disable_dcc_mrt),
.gfx10 =
{
.nbc_view = iview->nbc_view.valid ? &iview->nbc_view : NULL,
},
};
ac_set_mutable_cb_surface_fields(&pdev->info, &mutable_cb_state, &cb->ac);
}
static void
radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview, VkImageAspectFlags ds_aspects)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
unsigned level = iview->vk.base_mip_level;
bool stencil_only = iview->image->vk.format == VK_FORMAT_S8_UINT;
assert(vk_format_get_plane_count(iview->image->vk.format) == 1);
memset(ds, 0, sizeof(*ds));
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
/* Recommended value for better performance with 4x and 8x. */
ds->db_render_override2 = S_028010_DECOMPRESS_Z_ON_FLUSH(iview->image->vk.samples >= 4) |
S_028010_CENTROID_COMPUTATION_MODE(pdev->info.gfx_level >= GFX10_3);
const struct ac_ds_state ds_state = {
.surf = &iview->image->planes[0].surface,
.va = iview->image->bindings[0].addr,
.format = radv_format_to_pipe_format(iview->image->vk.format),
.width = iview->image->vk.extent.width,
.height = iview->image->vk.extent.height,
.level = level,
.num_levels = iview->image->vk.mip_levels,
.num_samples = iview->image->vk.samples,
.first_layer = iview->vk.base_array_layer,
.last_layer = max_slice,
.stencil_only = stencil_only,
.z_read_only = !(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT),
.stencil_read_only = !(ds_aspects & VK_IMAGE_ASPECT_STENCIL_BIT),
.htile_enabled = radv_htile_enabled(iview->image, level),
.htile_stencil_disabled = radv_image_tile_stencil_disabled(device, iview->image),
.vrs_enabled = radv_image_has_vrs_htile(device, iview->image),
};
ac_init_ds_surface(&pdev->info, &ds_state, &ds->ac);
const struct ac_mutable_ds_state mutable_ds_state = {
.ds = &ds->ac,
.format = radv_format_to_pipe_format(iview->image->vk.format),
.tc_compat_htile_enabled = radv_tc_compat_htile_enabled(iview->image, level),
.zrange_precision = true,
.no_d16_compression = true,
};
ac_set_mutable_ds_surface_fields(&pdev->info, &mutable_ds_state, &ds->ac);
if (pdev->info.gfx_level >= GFX11) {
radv_gfx11_set_db_render_control(device, iview->image->vk.samples, &ds->db_render_control);
}
}
void
radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer, struct radv_ds_buffer_info *ds)
{
const struct radeon_surf *surf = &image->planes[0].surface;
assert(image->vk.format == VK_FORMAT_D16_UNORM);
memset(ds, 0, sizeof(*ds));
ds->ac.db_z_info = S_028038_FORMAT(V_028040_Z_16) | S_028038_SW_MODE(surf->u.gfx9.swizzle_mode) |
S_028038_ZRANGE_PRECISION(1) | S_028038_TILE_SURFACE_ENABLE(1);
ds->ac.db_stencil_info = S_02803C_FORMAT(V_028044_STENCIL_INVALID);
ds->ac.db_depth_size = S_02801C_X_MAX(image->vk.extent.width - 1) | S_02801C_Y_MAX(image->vk.extent.height - 1);
ds->ac.u.gfx6.db_htile_data_base = radv_buffer_get_va(htile_buffer->bo) >> 8;
ds->ac.u.gfx6.db_htile_surface =
S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1) | S_028ABC_VRS_HTILE_ENCODING(V_028ABC_VRS_HTILE_4BIT_ENCODING);
}
void
radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
const VkImageViewCreateInfo *pCreateInfo,

14
src/amd/vulkan/radv_image_view.h
View file

@ -25,6 +25,17 @@ union radv_descriptor {
};
};
struct radv_color_buffer_info {
struct ac_cb_surface ac;
};
struct radv_ds_buffer_info {
struct ac_ds_surface ac;
uint32_t db_render_override2;
uint32_t db_render_control;
};
struct radv_image_view {
struct vk_image_view vk;
struct radv_image *image; /**< VkImageViewCreateInfo::image */
@ -90,4 +101,7 @@ void radv_make_texture_descriptor(struct radv_device *device, struct radv_image
uint32_t *fmask_state, const struct ac_surf_nbc_view *nbc_view,
const VkImageViewSlicedCreateInfoEXT *sliced_3d);
void radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_buffer,
struct radv_ds_buffer_info *ds);
#endif /* RADV_IMAGE_VIEW_H */