Commit graph

65762 commits

Author SHA1 Message Date
Alyssa Rosenzweig
dd85b50d18 treewide: use nir_break_if
Via Coccinelle patch and some manual hunk editing:

    @@
    expression b, E;
    @@

    -nir_push_if(b, E);
    -{
    -nir_jump(b, nir_jump_break);
    -}
    -nir_pop_if(b, NULL);
    +nir_break_if(b, E);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29877>
2024-06-26 19:07:35 +00:00
Danylo Piliaiev
653a4dc58f freedreno: Use LRZ feedback in gmem
(Same as in Turnip)

We set LRZ_FEEDBACK_EARLY_LRZ_LATE_Z mask for rendering pass after
HW binning because:
- Draws with EARLY_Z contributed to depth buffer in BINNING stage;
- Draws with LATE_Z is what usually disables LRZ.
- Draws with EARLY_LRZ_LATE_Z are the ones we want because they
  represent the common case of FS with "discard".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
2024-06-26 15:53:51 +00:00
Danylo Piliaiev
229bd7b9b9 freedreno: Describe LRZ feedback mechanism
Some draws do write depth but cannot contribute to LRZ during the BINNING pass
e.g. when fragment shader has "discard" in it, however they can contribute to
LRZ during the RENDERING pass via LRZ feedback meachanism. This may allow the
draws that follow to depth test against the updated LRZ, this is especially
important if such "bad" draws were at the start of the renderpass.

LRZ feedback happens during the RENDERING pass when LRZ_FEEDBACK_ZMODE_MASK
is set, if draw has a6xx_ztest_mode that has corresponding flag set in
LRZ_FEEDBACK_ZMODE_MASK - its depth values would be used for feedback.

LRZ feedback alongside with LRZ testing also works during sysmem rendering.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
2024-06-26 15:53:51 +00:00
Connor Abbott
337fb7dec2 ir3, tu, freedreno: Move early_preamble to ir3_shader
The ir3_info is reset by ir3_collect_shader_info() on the expectation
that all info is collected inside that function. This meant that we were
accidentally disabling early preamble. Re-enable it.

We keep a copy in ir3_info for shader statistics in the next commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29903>
2024-06-26 15:16:38 +00:00
Pierre-Eric Pelloux-Prayer
1a06494e65 radeonsi/tests: clarify the output when results changes
Print up to 10 results that are different from the baseline:

   2 new results:
     * spec@!opengl 1.0@rasterpos,Crash
     * spec@glsl-es-3.00@execution@built-in-functions@vs-packhalf2x16,Fail

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
d9f150f18b radeonsi/tests: update tests baseline
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
c97591b862 radeonsi: add gfx11 workaround for upgraded_depth
For unknown reasons, this is needed to avoid breaking
a bunch of tests:

   .*tex-miplevel-selection.*
   KHR-GL46.direct_state_access.framebuffers_texture_attachment,Fail
   KHR-GL46.direct_state_access.framebuffers_texture_layer_attachment,Fail
   .*.core.texture_cube_map_array.sampling

These failures were previously hidden by extra flushes in the
blitter that were removed in 969ed851.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
9d8073a5fd radeonsi/tests: add a shortcut to re-run only failing tests
'-t baseline' will only run the tests that are marked as failing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
27a841d335 radeonsi/tests: don't match gfx10_3 baseline for gfx10 family
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
19e342b877 radeonsi: handle DBG(TEX) after tc_compatible_htile is set
Otherwise the value printed might be incorrect.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
2024-06-26 14:02:13 +00:00
Karol Herbst
e5bb32da98 rusticl: enable v3d
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
0b85476d86 v3d: never replace a mapped bo
The application might have a pointer into the mapped bo.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
e5c4ea9323 v3d: fix MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
6768c81974 v3d: support variable shared memory
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
61b1a14e91 v3d: lower 64 bit ALUs
Even though rusticl won't advertise support for 64 bit ints, some of the
libclc builtins still use 64 bit operations to lower 32 bit ALU ops.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
7ff96fb5b0 v3d: lower CL alus
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
8f72e60c75 v3d: treat SHADER_KERNEL as SHADER_COMPUTE
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
3889a8e26c v3d: implement gallium APIs for OpenCL support
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:03 +00:00
Karol Herbst
a8f4ff691b rusticl/kernel/launch: fix global work offsets for 32 bit archs again
Fixes: bb2453c649 ("rusticl/kernel: move most of the code in launch inside the closure")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:02 +00:00
Karol Herbst
39721a7476 rusticl/mesa/screen: handle get_timestamp not set by driver
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:02 +00:00
Karol Herbst
bb33dbeeaa rusticl/mesa/context: handle clear_buffer not set by driver
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:02 +00:00
Karol Herbst
be4f3c2aa8 rusticl/device: require PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT for image support
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:02 +00:00
Karol Herbst
0fa4eaf6f6 gallium: add PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
2024-06-26 10:04:02 +00:00
Jianxun Zhang
3589035d61 iris: Disable predraw resolve (xe2)
Fixes piglit test:
arb_texture_barrier-blending-in-shader 32 1 1 64 7 -auto -fbo

src/intel/blorp/blorp_genX_exec.h:910: blorp_emit_ps_config:
Assertion `!"" "Invalid fast clear op"' failed.

Suggested by Kenneth Graunke <kenneth@whitecape.org>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:44 +00:00
Jianxun Zhang
31b48fd041 iris: Workaround: Don't allocate compressed bo from cache (xe2)
There should be some deeper causes to dig out. The bo-caching
system shouldn't affect the compression by design.

Fixes:
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear_mipmap_linear

The two cases can pass if we run them respectively. But once they
are fed to glcts in a test case list file (test.list) to run together,
the second test case hangs for a while and eventually fails, regardless
which of them is the second.

./glcts --deqp-caselist-file=test.list

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Jianxun Zhang
8a815c83c2 iris: Update synchronization of fast clear (xe2)
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Jianxun Zhang
b6f9702cf1 iris: Disable PAT-based compression on depth surfaces (xe2)
Fix: Piglit
PIGLIT_PLATFORM="gbm" piglit/bin/getteximage-depth -auto -fbo

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Jianxun Zhang
9cd97b6137 iris: Add more restrictions on compression (Xe2)
Also move the declaration of a local variable to where
it is going to use.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Jianxun Zhang
66fa1c5ddd iris: Limit FCV_CCS_E to platforms that enable it
We want to keep aux state always in compressed and no clear,
but the write behavior of FCV will change it to compressed and
clear. Reuse old CCS_E on Xe2 to workaround it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8785

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Jianxun Zhang
df006bba02 iris: Update aux state for color fast clears (xe2)
The texturing and rendering preparation functions restrict
fast clear support in some cases to account for limitations
on prior platforms. Instead of updating those checks to avoid
resolves on Xe2, we can bypass them by representing the aux
state of a fast-cleared surface as compressed-no-clear. This
is valid because there is no longer a bit pattern which
references a clear value stored outside of the aux surface.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Daniel Stone
9eeaa4618f egl/gbm: Enable RGBA configs
Doing this is harmless since we operate on an allowlist of pipe_configs
anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
2024-06-25 19:30:12 +00:00
Daniel Stone
5ca85d75c0 dri: Fix BGR format exclusion
The check we had for BGR vs. RGB formats was testing completely the
wrong thing. Fix it so we can restore the previous set of configs we
expose to the frontend, which also fixes surfaceless platform on s390x.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: ad0edea53a ("st/dri: Check format properties from format helpers")
Closes: mesa/mesa#11360
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29837>
2024-06-25 19:30:12 +00:00
José Roberto de Souza
5b8b4f7878 intel/dev: Add engine_class_supported_count to intel_device_info
Next patch will need to frequently get the count of supported engine
for compute and copy engines, so to reduce the overhead of doing
KMD queries at every call here caching this information into
intel_device_info struct.

With that ANV and Iris would need to set this information as intel/dev
can't depend on intel/common, so here adding a single function
to update intel_device_info with all fields filled by intel/common
functions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29899>
2024-06-25 14:16:45 +00:00
Daniel Lundqvist
3274af99bf radeonsi: Fix unused variable when LLVM is not used for AMD.
use_aco is only used when define AMD_LLVM_AVAILABLE is set. Inline
it into its only user.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29862>
2024-06-25 03:45:16 +00:00
Karol Herbst
47b1241251 rusticl/queue: run rustfmt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29880>
2024-06-25 01:39:46 +00:00
Karol Herbst
9d458b7fc1 rusticl/queue: gracefully stop the worker thread
Ohterwise we might get caught up in memory corruptions I still have no
explanation for.

Fixes spontanous crashes with radeonsi and the OpenCL CTS.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29880>
2024-06-25 01:39:46 +00:00
Dave Airlie
6ebc94250c gallivm: split out generating LLVM Mattrs
This will be reused in the orc jit

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29869>
2024-06-25 09:35:28 +10:00
Dave Airlie
76e2ceb8f8 gallivm: export target init code for orc-jit to reuse
It doesn't need the wrapper since it already has a singleton

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29869>
2024-06-25 09:35:28 +10:00
Dave Airlie
1f4268b53e gallivm: make lp_bld_coro.h c++ include safe.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29869>
2024-06-25 09:35:28 +10:00
Dave Airlie
63d2bb103a gallivm: split some code out from init module.
In order to introduce orc some code should be split out where
it can be reused.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29869>
2024-06-25 09:35:28 +10:00
Dave Airlie
05dd12b9a5 gallivm: move ppc denorm disable to inline
This just puts it out of the way

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29869>
2024-06-25 09:35:28 +10:00
Paulo Zanoni
5c18ccd2d3 anv/sparse: reject 1D sparse residency images
The Vulkan spec splits sparse resources in two different features:
sparse binding and sparse residency.

Sparse binding is much simpler. It requires the resources to be fully
bound before being used and it treats them as a black box. We're
required to support sparse binding for all the formats that are
supported by non-sparse, but that's easy beacause this feature is
simpler.

Now sparse residency is the one where we're allowed to partially bind
resources, and the one that comes with more complicated features such
as block shapes and non-opaque binding of images. This feature is
subdivided into:
  - sparseResidencyBuffer
  - sparseResidencyImage2D
  - sparseResidencyImage3D
  - sparseResidency{2,4,8,16}Samples (which refers to 2D images)

Notice that there's no sparseResidencyImage1D. And if you read the
specs it's clear that sparse residency is meant for non-1D images.
Still, supporting it didn't require any extra effort in Anv so we just
did it.

That's until we started running GL CTS tests on Zink. There's a CTS
test that checks for the standard block shapes. It creates 1D images
and expects the block shapes for them to be the standard 2D block
shapes. While we could very well just patch
anv_sparse_calc_image_format_properties() to return the standard 2D
block shapes for 1D images, that's just wrong (block shapes for 1D
images are just line segments, not rectangles!) so let's just reject
this all until maybe one day Vulkan defines sparseResidencyImage1D and
we get GL_ARB_sparse_texture3 to match it, or somebody decides to
change the GL CTS test.

Testcase: KHR-GL46.sparse_texture2_tests.StandardPageSizesTestCase
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29337>
2024-06-24 17:54:30 +00:00
Mike Blumenkrantz
35fd98f2d9 radeonsi: enable compute pbo blits
this probably needs better tuning by experts, but it massively improves
perf in a number of cases

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29842>
2024-06-24 15:48:37 +00:00
Karol Herbst
a7ad53d550 radeonsi: set bo_size for user memory allocations
Otherwise the assert in si_set_shader_buffer could trigger for blits
through clear_buffer on user resources.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29867>
2024-06-24 15:04:25 +00:00
Tapani Pälli
7934b70ff1 isl/iris/anv: provide drirc toggle intel_sampler_route_to_lsc
Some applications may benefit from this while some can get a performance
hit. Default to false and make it possible to toggle only for selected
workloads.

See workaround 14022483228 for some measurements.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29760>
2024-06-24 09:23:07 +00:00
Collabora's Gfx CI Team
cdf3228f88 Uprev Piglit to fdf3fc09deb6beecdf212e65a16c645112540b59
cf8daaf5ba...fdf3fc09de

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29684>
2024-06-24 07:10:48 +00:00
Karol Herbst
cdd604583f rusticl/icd: rename all entry points to the actual correct name
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29855>
2024-06-22 23:40:15 +00:00
Karol Herbst
be090abf2e rusticl: add bsymbolic to linker flags
This will prevent the dynamic loader to pick the wrong function once we
rename things to the proper API names.

In any case, this should have been done all along anyway.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29855>
2024-06-22 23:40:15 +00:00
Rémi Bernon
8d210ae232 zink: Add VKAPI_PTR specifier to zink_stub_function_not_loaded.
To avoid a warning with clang when the function is cast to stdcall
function pointer on Windows.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29856>
2024-06-22 12:20:04 +02:00
Juan A. Suarez Romero
d4dcbaf825 util: do not access member of a NULL structure
Check if the structure is NULL before trying to get access to its
members.

This has been detected by the Undefined Behaviour Sanitizer (UBSan).

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29772>
2024-06-21 21:07:05 +00:00