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freedreno: Use LRZ feedback in gmem

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(Same as in Turnip)

We set LRZ_FEEDBACK_EARLY_LRZ_LATE_Z mask for rendering pass after
HW binning because:
- Draws with EARLY_Z contributed to depth buffer in BINNING stage;
- Draws with LATE_Z is what usually disables LRZ.
- Draws with EARLY_LRZ_LATE_Z are the ones we want because they
  represent the common case of FS with "discard".

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25345>
This commit is contained in:
Danylo Piliaiev 2023-09-22 12:17:05 +02:00 • committed by Marge Bot
parent 02b1d23fed
commit 653a4dc58f
1 changed files with 14 additions and 6 deletions
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20
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -1021,7 +1021,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
set_bin_size<CHIP>(ring, gmem, {
.render_mode = BINNING_PASS,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
.lrz_feedback_zmode_mask = LRZ_FEEDBACK_NONE,
});
update_render_cntl<CHIP>(batch, pfb, true);
emit_binning_pass(batch);
@ -1035,12 +1035,13 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
* the reset of these cmds:
*/
// NOTE a618 not setting .FORCE_LRZ_WRITE_DIS ..
set_bin_size<CHIP>(ring, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = true,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE,
});
OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
@ -1060,8 +1061,12 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
set_bin_size<CHIP>(ring, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
.lrz_feedback_zmode_mask =
screen->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE,
});
}
@ -1138,8 +1143,11 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
set_bin_size<CHIP>(ring, gmem, {
.render_mode = RENDERING_PASS,
.force_lrz_write_dis = !ctx->screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = (a6xx_lrz_feedback_mask) (LRZ_FEEDBACK_LATE_Z | LRZ_FEEDBACK_EARLY_LRZ_LATE_Z),
.lrz_feedback_zmode_mask = ctx->screen->info->a6xx.has_lrz_feedback
? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
: LRZ_FEEDBACK_NONE,
});
OUT_PKT7(ring, CP_SET_MODE, 1);