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iris: Update synchronization of fast clear (xe2)

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Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
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Jianxun Zhang 2024-05-05 19:11:43 -07:00 • committed by Marge Bot
parent 6073f091bb
commit 8a815c83c2
1 changed files with 10 additions and 1 deletions
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11
src/gallium/drivers/iris/iris_clear.c
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@ -272,10 +272,19 @@ fast_clear_color(struct iris_context *ice,
* contents of the previous draw hit the render target before we resolve
* and again afterwards to ensure that the resolve is complete before we
* do any more regular drawing.
*
* On Xe2+:
* From Bspec 57340 (r59562):
*
* Synchronization:
* Due to interaction of scaled clearing rectangle with pixel
* scoreboard, we require one of the following commands to be issued.
*
* Requiring tile cache flush bit has been dropped since Xe2.
*/
iris_emit_end_of_pipe_sync(batch, "fast clear: pre-flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_TILE_CACHE_FLUSH |
(devinfo->verx10 < 200 ? PIPE_CONTROL_TILE_CACHE_FLUSH : 0) |
(devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) |
(devinfo->verx10 == 125 ? PIPE_CONTROL_FLUSH_HDC |
PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |