Use lower_tg4_offsets to take care of explicit offsets, and just swizzle
the texels in the order defined by textureGather*
Fixes: 46c9239c11 ("pvr, pco: initial texture gather support with gather sampler")
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
(cherry picked from commit 56b8dc92a9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Increase past the minimum required by the Vulkan Spec to fix tests. This
was needed due to Zink requirements which splits
`maxPerStageDescriptorStorageBuffers` between atomic buffers and
`MaxShaderStorageBlocks`.
Fixes the following GLES conformance tests:
KHR-GLES31.core.compute_shader.resources-max
KHR-GLES31.core.draw_indirect.advanced-twoPass-Compute-arrays
KHR-GLES31.core.shader_image_load_store.advanced-sync-vertexArray
KHR-GLES31.core.shader_image_load_store.basic-allTargets-store-cs
KHR-GLES31.core.shader_image_load_store.basic-allTargets-store-fs
KHR-GLES31.core.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-int
KHR-GLES31.core.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case1-cs
KHR-GLES31.core.shader_storage_buffer_object.basic-stdLayout_UBO_SSBO-case2-cs
dEQP-GLES31.functional.draw_indirect.compute_interop.combined.drawelements_compute_cmd_and_data_and_indices
dEQP-GLES31.functional.synchronization.in_invocation.ssbo_alias_overwrite
dEQP-GLES31.functional.synchronization.in_invocation.ssbo_alias_write
dEQP-GLES31.functional.synchronization.in_invocation.ssbo_atomic_alias_overwrite
dEQP-GLES31.functional.synchronization.in_invocation.ssbo_atomic_alias_write
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_atomic_multiple_write_read
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.ssbo_multiple_write_read
dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_alias_overwrite
dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_alias_write
dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_alias_overwrite
dEQP-GLES31.functional.synchronization.inter_invocation.ssbo_atomic_alias_write
Backport-to: 26.0
Signed-off-by: Arjob Mukherjee <arjob.mukherjee@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
(cherry picked from commit 35f57a2739)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
ac_nir_optimize_outputs() might pack user varyings into the color
built-ins. If this happens we skip adding clamping to the
components that contain the user varying.
This change also fixes a second bug where a color built-in can be
packed into a non-color slot and was no longer being clamped.
Fixes: 3777a5d7 ("radeonsi: assign param export indices before compilation")
Closes: #14443
Reviewed-by: Marek Olšák <maraeo@gmail.com>
(cherry picked from commit a42c55da46)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
This should only consider valid entries, not loop over the entire array.
In addition the array size was wrong before.
Fixes: 779edc0759 ("frontends/va: Correctly derive HEVC StCurrBefore, StCurrAfter and LtCurr")
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
(cherry picked from commit c2a4fa33b8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
When r300_pick_vertex_shader switches to a WPOS variant, it only dirtied
rs_block_state, leaving vs_state with a stale code size. This caused
cs_count warnings (offset of -4 for one extra VS instruction) but was
mostly harmless since the emitted packet stream still used the current
shader.
Factor the VS code dirtying out of r300_bind_vs_state into a helper and
call it when selecting a new variant too.
Fixes: 806dcf9db7 ("r300: only output wpos in vertex shaders when needed")
(cherry picked from commit cc7be8433a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
r300_simple_msaa_resolve used to patch srcsurf->pitch with the resolve
destination's tiling bits before passing the surface to the blitter.
That worked when set_framebuffer_state kept the same pipe_surface
pointer, so r300_get_nonnull_cb returned the patched object.
After the de-pointerization, r300_framebuffer_init creates a fresh
r300_surface from the pipe_surface template, discarding the pitch
modification. The hardware then uses the MSAA source tiling for
R300_RB3D_COLORPITCH0, leading to corruption.
Move the tiling override into r300_emit_fb_state and override the tiling
bits of COLORPITCH from the destination surface at emit time.
Fixes: 2eb45daa9c ("gallium: de-pointerize pipe_surface")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15303
(cherry picked from commit 416da54cce)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Sampling coeffs with trilinear filtering will output 2x sets of data.
Whether bilinear or trilinear filtering is in use can't be determined
without checking state words, so unconditionally reserve 2x to avoid
clobbering output regs.
Fixes: 7df32ba09d ("pco: initial texture/sampler compiler support")
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Tested-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
(cherry picked from commit af1669d9e2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
The index buffer and index buffer size don't affect whether or not we're
actually doing indexed rendering so we should just emit them whenever
they change. Otherwise, if someone sets an index buffer and then does a
non-indexed draw and then an indexed draw, the first draw will clear the
dirty bits without setting the index buffer registers and the second
draw won't know to re-emit them.
Fixes: 5544d39f44 ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
(cherry picked from commit 9c8e8ed655)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
The Vulkan spec says:
"VUID-vkCmdExecuteGeneratedCommandsEXT-None-11062
If a rendering pass is currently active, the view mask must be 0."
So, it's invalid with VK_EXT_device_generated_commands but it's allowed
in DX12, it seems we missed this during the spec review.
Crimson Desert uses this and emulating in vkd3d-proton would be complex,
so let's re-introduce this support only for vkd3d-proton.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 782254b820)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
This reverts commit b83a931cb1 as it causes
regressions with dirty rects enabled on some HW platforms that signal
out of order completion and require individual fence objects per slice
Fixes: b83a931cb1 ("d3d12: Video sliced encode: Use same ID3D12Fence/different per slice values as optimization")
Reviewed-by: Pohsiang (John) Hsu <pohhsu@microsoft.com>
(cherry picked from commit fb13c044a8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Casting a negative float to uint64_t is undefined behavior. GCC 15 with
-O2 produces 0xFFFFFFFFFFFFFFFF for (uint64_t)(-32767.5f), causing snorm
clear values to be packed incorrectly (e.g. 0xFFFF instead of 0x8001 for
snorm16 -1.0). This results in wrong DCC comp-to-single clear colors and
~966 CTS snorm multisample_resolve test failures.
Fix by casting through int64_t first, which is well-defined (truncation
toward zero) and preserves the two's complement bit pattern.
Fixes: 585c25be1e ("radv: fix color conversions for normalized uint/sint formats")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 2595940b0d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Because of a previous refactor, pco_last_igrp was incorrectly changed to return
the first entry in a linked list instead of the last. Update pco_last_igrp to
return the last entry in a linked list.
The following CTS tests now pass:
dEQP-GLES3.functional.shaders.switch.conditional_fall_through_2_dynamic_fragment
dEQP-GLES3.functional.shaders.switch.conditional_fall_through_dynamic_fragment
dEQP-GLES3.functional.shaders.switch.conditional_fall_through_uniform_fragment
Fixes: 719ece42c0 ("pco: Switch back to util/list")
Signed-off-by: Duncan Brawley <duncan.brawley@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
(cherry picked from commit 7428af29f6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Just like the fix for nvk, just drop this in the GL driver as well.
Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
(cherry picked from commit 3f5d54ab8c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Repairing SSA was creating invalid PHI nodes with source swizzles !=
BI_SWIZZLE_H01. PHI sources can't have non-identity swizzles.
In most cases the repair logic only replaces sources, in which case the
swizzle is taken from the old source that is getting replaced. However,
in add_phi_operands there is no old source because the phi is new, and
so the result from resolve_read is assigned directly. This falsely
carries over the destination swizzle to the source.
Since it never makes sense for resolve_read to carry over the swizzle
from the instruction writing the value, we can make it so that
resolve_read always returns the identity swizzle on indices.
resolve_read returns one of:
- An index stored by record_write
- An index created by bi_temp_like
- The result of a recursive resolve_read call
bi_temp_like already correctly sets the swizzle to H01. Setting it in
record_write leads to both base cases returning the desired swizzle.
Fixes: dd94d183 ("pan/bi: Fixup bi_repair_ssa.c for bi")
Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
(cherry picked from commit fcfc580f67)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
ret was read after the timeout check, so breaking on timeout returned 0
instead of the actual fence status, potentially reporting a signaled
fence when it was still pending.
Fixes: 441f01e778 ("freedreno/drm/virtio: Drop blocking in host")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
(cherry picked from commit 97baa27dad)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
Fixes two bugs in the WAIT_FENCE polling loop:
1. Break on timeout returned VK_SUCCESS because ret was read too late.
2. UINT64_MAX timeout_ns overflowed end_time, causing immediate exit.
Fix by reading rsp->ret before the timeout check and using
OS_TIMEOUT_INFINITE (like virtio_pipe_wait in freedreno) to avoid
overflow.
This prevents premature BO teardown during host-side fault recovery.
Fixes: f17c5297d7 ("tu: Add virtgpu support")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
(cherry picked from commit dad72b414b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
New IB print will assert reserved packet field to be zero.
Fixes: 1c75cd958f ("ac: enable the new auto-generated CP packet parser")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 89c1bf34ed)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
By default crocus precompiles shaders, to avoid stuttering at screens,
caused by compiling shaders at the drawing phase.
Unfortunately at intel Gen 6 and higher the precompiled version of the
fragment shaders is not used and every fragment shader is compiled twice.
These double fragment shaders also are added to the memory cache
and disk cache.
This is caused by setting wrong values to variables at the key during
precompiling at routine crocus_create_fs_state() at src/gallium/drivers/crocus/crocus_program.c,
which differ from values at crocus_populate_fs_key() at src/gallium/drivers/crocus/crocus_state.c.
This commit solves 3 problems:
it adjusts the predicted value 'input_slots_valid' at Gen 6
it adjusts the predicted value 'ignore_sample_mask_out' at Gen 6 and higher
it predicts the value 'multisample_fbo' , which helps if samplemask is used
Cc: mesa-stable
Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 686266d2f1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
PANVK_DEBUG_HSR_PREPASS and PANVK_DEBUG_NO_EXTENDED_VA_RANGE have the
same value, meaning they both get toggled when one is.
This commit moves PANVK_DEBUG_HSR_PREPASS to the following value.
Fixes: 2d9be41706 ("panvk/v13: Support HSR Prepass")
Reviewed-by: John Anthony <john.anthony@arm.com>
(cherry picked from commit 82592433e6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
This can be used to workaround problem cases with application
controlled subgroup size.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit c105366165)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41268>
The previous fix was incomplete because if the same graphics pipeline
and the same PS epilog are rebind after vkCmdExecuteCommands(), the PS
epilog state wouldn't be re-emitted, and it will use a wrong VA (in case
both fragment shader user SGPRs aren't similar either).
Resetting the PS epilog to NULL in the primary should prevent any
issues, but this tracking still need to be improved because it caused
two issues recently.
Fixes: 1a00587c44 ("radv: fix a GPU hang with PS epilogs and secondary command buffers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15176
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit a73fc90bcd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
Remove the TU_DEBUG_FLUSHALL option that was force-enabled for a8xx chips.
The problematic CTS cases that required it were failing due to indirect
draw commands sourcing draw data from buffers whose content was prepared
by compute tasks.
Up until a8xx, firmware was managing an implicit wait before any indirect
draw parameters were read, with a delayed CP_WAIT_FOR_ME emitted only when
necessary or on devices enabling indirect_draw_wfm_quirk due to bugged
firmware. That implicit wait is gone on a8xx, so CP_WAIT_FOR_ME should be
emitted immediately, which also matches behavior of the proprietary driver.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
(cherry picked from commit 9931034dca)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
The post-processing infrastructure is showing it's age; it's written
using TGSI, which has been on the way out for a long time. There's also
few actually useful filters in there, and there are better tools out
there to inject shaders into applications.
Let's mark this as deprecated, so we can delete it in the future. Having
a deprecation period makes it easier for any potential users to find
alternatives in a timely matter.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
StackSizePerRay is the RTDispatchGlobals::AsyncStackSize and
DisableRTGlobalsKnownValues is to interpret how many Max BVH levels we
need to use. It's not relevant to Vulkan, since we have just 2 fixed BVH
levels.
Fixes: cb423ee6 ("anv: Fix Wa_14021821874, Wa_14018813551, Wa_14026600921")
Fixes: c1a44e8d ("anv: force StackIDControl value for Wa_14021821874")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit 7a627fa8f3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
I ran into this case where genX(cmd_buffer_emit_bt_pool_base_address)
was returning immediately because it considered an RCS engine
emulating a compute queue as neither a render nor a compute queue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit d581b7282b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
Probably worked because we could always reach to things through the
binding table and the index was the same.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 3256fab5a3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
For some reason the android builders started noticing...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit f6306198d0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
The Vulkan spec states that if VK_KHR_shader_clock is supported,
shaderSubgroupClock is a required feature. So let's not enable that
extension unless we can...
Fixes: e9c2c32409 ("panvk: enable VK_KHR_shader_clock")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit c8ae72f51d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
The Vulkan spec states that if VK_ARM_shader_core_builtins is supported,
shaderCoreBuiltins is a required feature. So let's not enable that
extension unless we can...
Fixes: dff1d91c64 ("panvk: Enable VK_ARM_shader_core_builtins")
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 8cb89853b8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
This hasn't been supported since the TGSI envvar was ripped out. When
converted to NIR, we don't see these instructions at all.
Fixes: c3cbe610df ("nouveau: Delete the NV50_PROG_USE_TGSI env var.")
Reviewed-by: Marek Olšák <maraeo@gmail.com>
(cherry picked from commit b062062430)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
We can't expose large texel-buffers if we don't emit the high bits.
Whoopsie!
Fixes: 4db7958edc ("pan/bi: Change texel buffer limits")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit 57a80ff78c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
A few cases of UINT32_MAX were missed, whoops.
Fixes: c2c91e78fd ("pan/layout: Allow bigger size/surface stride on v12+")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
(cherry picked from commit 69b8372fbf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
This change was tested on plam and cayman. Here are the tests fixed:
spec/arb_gl_spirv/execution/uniform/atomic-uint-aoa-cs: fail pass
spec/arb_gl_spirv/execution/uniform/atomic-uint-aoa-fs: fail pass
spec/arb_gl_spirv/execution/uniform/atomic-uint-array-cs: fail pass
spec/arb_gl_spirv/execution/uniform/atomic-uint-array-fs: fail pass
spec/arb_gl_spirv/execution/uniform/atomic-uint-cs: fail pass
spec/arb_gl_spirv/execution/uniform/atomic-uint-fs: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 0deac18581)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
This change adds a minimal support for gl_PointSize to
be used alongside gl_ClipDistance/gl_CullDistance.
This change was tested on palm and cayman. Here is the test fixed:
khr-gl4[5-6]/gl_spirv/spirv_validation_builtin_variable_decorations_test: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 032a2bdc1e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
The atomic offset implementation was incomplete.
This change was tested on cayman, it fixes all the
variants of this test:
khr-gl4[2-6]/shader_atomic_counters/advanced-usage-multi-stage: fail pass
khr-gles31/core/shader_atomic_counters/advanced-usage-multi-stage: fail pass
Fixes: 06993e4ee3 ("r600: add support for hw atomic counters. (v3)")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 48902771ad)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
This change is inspired by b56f47611a ("radeonsi: fix
alpha-to-coverage + alpha-to-one used together for
gfx6-10.3") and implements the same algorithm.
This change was tested on rv770, palm and cayman. Here are the tests fixed:
spec/arb_framebuffer_object/execution/msaa-alpha-to-coverage_alpha-to-one: fail pass
spec/arb_framebuffer_object/execution/msaa-alpha-to-coverage_alpha-to-one_write-z: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit 7513f48edf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41104>
