Commit graph

159753 commits

Author SHA1 Message Date
Chad Versace
ca687bc263 venus: Add macros VN_SET_CORE_*
Used to refactor vn_physical_device.c.  The new code easier to read and
has less duplication.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
5932358447 venus: Refactor VN_ADD_TO_PNEXT
Motivation is easier sorting and readability.

- In VN_ADD_TO_PNEXT_OF, re-arrange params to allow sorting. Param1 is
  invariant in each block. Param2 is sType.

- In VN_ADD_EXT_TO_PNEXT_OF, make its initial params match those of
  VN_ADD_TO_PNEXT_OF.

- Then sort the macro calls.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Chad Versace
7c02730ed3 venus: Rename some feature/property structs
Make the variable name more closely match the type name.
This also allows them to sort correctly.

  argb_4444_formats     -> _4444_formats
  eight_bit_storage     -> _8bit_storage
  sixteen_bit_storage   -> _16bit_storage

While touching vn_physical_device.[ch], also run clang-format.

Signed-off-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18158>
2022-09-14 15:32:22 +00:00
Mike Blumenkrantz
db192c0883 zink: handle split acquire/present
if the swapchain image is acquired in a different cmdbuf than it gets
presented with, the acquire semaphore will have already been submitted
by this point, and the swapchain should be flagged as such

cc: mesa-stable

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18557>
2022-09-14 15:09:44 +00:00
Mike Blumenkrantz
5505811f64 radv: avoid bottlenecking on sequential sparse buffer binds
it's more costly to submit individual sparse buffer binds than to
merge them and submit bigger binds, so try to pre-compare and flatten
out the bind array as much as possible to reduce ioctl counts

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18507>
2022-09-14 14:40:02 +00:00
Mike Blumenkrantz
4e4d91a79d docs: add more features
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>
2022-09-14 14:19:05 +00:00
Mike Blumenkrantz
054c9e708a lavapipe: ARM/EXT_rasterization_order_attachment_access
another no-op

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>
2022-09-14 14:19:05 +00:00
Mike Blumenkrantz
bb3f3c6502 lavapipe: VK_EXT_attachment_feedback_loop_layout
no-op

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17956>
2022-09-14 14:19:05 +00:00
Iago Toral Quiroga
ab378b9ce5 v3dv: expose VK_EXT_load_store_op_none
This extension adds new NONE attachment load / store operations,
which are identical to the DONT_CARE variants with the difference
that DONT_CARE doesn't ensure that the original contents of the
memory within the render area are preserved and these new versions
do (with some caveats).

Our implementation was not destroying data with DONT_CARE anyway
so we already support the new semantics. Our implementation is
such that we don't need to do anything specific with the new
operations and the current behavior will do what is expected.

We pass all the tests under:
dEQP-VK.renderpass*.load_store_op_none.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18570>
2022-09-14 13:48:46 +00:00
Iago Toral Quiroga
5e8196e756 v3dv: don't load an attachment for unaligned render area if we are not storing
If the render area is not aligned to tile boundaries it means we have partially
covered tiles in the framebuffer. In this case, we always need to load the tile
buffer from memory in order to preserve the contents outside the render area
on the tile buffer store. However, if in this scenario we know we won't be
storing the tile buffer we can skip the load safely.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18570>
2022-09-14 13:48:45 +00:00
Danylo Piliaiev
34109c8c10 turnip: implement VK_EXT_multi_draw
vkoverhead running:
    * draw numbers are reported as thousands of operations per second
    * percentages for draw cases are relative to 'draw'
   0, draw,                                      29151,        100.0%
   1, draw_multi,                                35449,        121.6%
   2, draw_vertex,                               28907,        99.2%
   3, draw_multi_vertex,                         56658,        194.4%

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11502>
2022-09-14 13:18:02 +00:00
Rajnesh Kanwal
2e93833224 pvr: Fix multiple file descriptor leaks.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reported-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18594>
2022-09-14 13:08:29 +00:00
Connor Abbott
201851a3d1 tu: Initial implementation of VK_EXT_inline_uniform_block
This is a trivial implementation where we just insert a UBO descriptor
pointing to the actual data and then treat it as a normal UBO everywhere
else. In theory an indirect CP_LOAD_STATE would be more efficient than
ldc.k to preload inline uniform blocks to constants. However we will
always need the UBO descriptor anyway, even if we lower the limits
enough to always be able to preload them, because with variable pointers
we may have a pointer that could be to either an inline uniform block or
regular uniform block. So, using an indirect CP_LOAD_STATE should be an
optimization on top of this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>
2022-09-14 12:46:01 +00:00
Connor Abbott
15f3274ea6 tu: Don't preload variable-count descriptors
We don't know how many descriptors will actually be valid, which could
lead to preloading descriptors out-of-bounds of the descriptor size.
This was leading to GPU hangs on some tests once we enabled inline
uniforms.

Fixes: d9fcf5de55 ("turnip: Enable nonuniform descriptor indexing")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>
2022-09-14 12:46:01 +00:00
Connor Abbott
05266333a0 tu: Fix descriptor set size bounds
This old code looks like it was left around from anv. Make it use the
limits the rest of the code uses.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17960>
2022-09-14 12:46:00 +00:00
Rhys Perry
b301c33f65 nir/algebraic: optimize fabs(bcsel(b, fneg(a), a))
fossil-db (Sienna Cichlid):
Totals from 207 (0.15% of 134913) affected shaders:
VGPRs: 7152 -> 6928 (-3.13%)
CodeSize: 762404 -> 752888 (-1.25%)
MaxWaves: 6138 -> 6146 (+0.13%)
Instrs: 144031 -> 142184 (-1.28%)
Latency: 817783 -> 807286 (-1.28%)
InvThroughput: 151031 -> 147497 (-2.34%)
VClause: 1490 -> 1453 (-2.48%)
SClause: 3357 -> 3331 (-0.77%); split: -0.92%, +0.15%
Copies: 9632 -> 9555 (-0.80%); split: -0.81%, +0.01%
Branches: 4306 -> 4270 (-0.84%)
PreSGPRs: 11232 -> 11218 (-0.12%); split: -0.15%, +0.03%
PreVGPRs: 6307 -> 6121 (-2.95%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14772>
2022-09-14 12:16:07 +00:00
Danylo Piliaiev
33e60798e1 ir3: Prevent reordering movmsk with kill
`kill` changes which fibers are active, thus reodering instructions
which depend on which fibers are active - is wrong.

The issue was hidden because only `ballot(true)` is translated to movmsk
immidiately, while others are passed as MACRO and don't properly
take part in ir3_sched (which does the reordering).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7162

Fixes CTS test (on gen3+):
 dEQP-VK.spirv_assembly.instruction.terminate_invocation.terminate.subgroup_ballot

Fixes: b1b80c06a7
("ir3: Implement nir subgroup intrinsics")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18413>
2022-09-14 11:56:28 +00:00
Frank Binns
b97b15d762 pvr: add required pixel formats
As per section 33.3 ("Required Format Support") of the Vulkan 1.0 spec - see
tables 42 to 52.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18572>
2022-09-14 11:13:42 +00:00
Tapani Pälli
27c5b93d37 iris: disable preemption on VFG, Wa_14015207028 for DG2
This workaround disables batch level preemption for Polygon,
Trifan and Lineloop primitive topologies.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
2022-09-14 10:01:23 +00:00
Tapani Pälli
ddcd6b3834 anv: disable preemption on VFG, Wa_14015207028 for DG2
This workaround disables batch level preemption for Polygon,
Trifan and Lineloop primitive topologies.

v2: cleanups (José)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
2022-09-14 10:01:23 +00:00
Tapani Pälli
d5d4604aa6 intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register
This can be used to disable batch preemption on DG2+ either
completely or with selected primitive topologies.

Commit adds bit explicitly for Polygon, Trifan and LineLoop
topologies for Wa_14015207028.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
2022-09-14 10:01:23 +00:00
Eric Engestrom
5bfca00d31 broadcom: fix dependencies in static_library() calls
The first argument is the name of the library, and the second argument
is the list of files; those two got a bit mixed up.

Fixes: 1ae8018a6a ("meson: Add support for the vc4 driver.")
Fixes: 4f3e380fa0 ("meson: Add support for the vc5 driver.")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18593>
2022-09-14 09:38:28 +00:00
Pavel Ondračka
0deca8bef8 r300: add some synchronization for KIL
Set texture semaphore wait at the first control flow instruction
after the KIL.

Fixes: dEQP-GLES2.functional.shaders.discard.dynamic_loop_always

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18576>
2022-09-14 09:27:54 +00:00
Konstantin Seurer
6a19950b61 radv: Explicitly store the VA of accel structs
Gets rid of a bit of code and fixes the RRA accel_struct_vas table if
the BO is freed before vkDestroyAccelerationStructureKHR is called.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>
2022-09-14 09:05:25 +00:00
Konstantin Seurer
7da66f8f25 radv/rra: Replace aliasing assert with a warning
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>
2022-09-14 09:05:25 +00:00
Konstantin Seurer
916621e5a5 radv: Make the radv_buffer_get_va parameter const
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>
2022-09-14 09:05:25 +00:00
Konstantin Seurer
d94cb8b595 radv/rra: Remove redundant bounds validation
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>
2022-09-14 09:05:25 +00:00
Konstantin Seurer
97d8bb9bc6 radv/rra: Map accel struct VAs to handles
When validating a BVH, rra_validate_node uses _mesa_hash_table_u64_search to lookup, whether a BLAS pointer is valid. Since _mesa_hash_table_u64_search returns the data field of the found entry, we need to populate it. Otherwise, the NULL-check won't work.

Fixes: 5749806 ("radv: Add Radeon Raytracing Analyzer trace dumping utilities")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18530>
2022-09-14 09:05:25 +00:00
Corentin Noël
ba9c73f9d4 virgl/ci: Update virglrenderer
Update virglrenderer past to version 0.10.1

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18418>
2022-09-14 06:39:29 +00:00
Yonggang Luo
eec1e728c5 c11: Update the values of enum mtx_plain, mtx_recursive, mtx_timed to make sure mtx_recursive != mtx_plain | mtx_recursive
According to c11 standards, there is 4 variant of mtx_init parameter,
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive

Directly use mtx_recursive is not a thing, so we need make sure mtx_plain and mtx_plain|mtx_recursive are not equal,
So now we choose the values from Android c11 threads.h for enum mtx_plain, mtx_recursive, mtx_timed, to make sure
c11/threads.h be more c11 conformance, and can raise error when the type parameter of mtx_init are not one of
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
2022-09-14 02:46:51 +00:00
Yonggang Luo
0894762cb8 svga: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
2022-09-14 02:46:51 +00:00
Yonggang Luo
e1139a3fc3 radeonsi: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
2022-09-14 02:46:51 +00:00
Yonggang Luo
77e8b5bbb0 mesa: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
2022-09-14 02:46:51 +00:00
Rob Clark
8192772c0a freedreno: Remap high/norm/low priorities
At the gallium level, we only have three priorities.  But if kernel
supports preemption we'll have 3*nr_rings priority levels.  We'd prefer
to have the priorities that userspace picks be distributed over the
entire range of priorities so that preemption can work.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
2022-09-14 02:06:27 +00:00
Rob Clark
2451c30c11 freedreno: nr_rings -> nr_priorities
This was renamed in the UABI header over a year ago, see
fc40e5e10c3b ("drm/msm: Utilize gpu scheduler priorities")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
2022-09-14 02:06:27 +00:00
Rob Clark
8e890a8b58 freedreno: Misc indent fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
2022-09-14 02:06:27 +00:00
Chia-I Wu
43c53e3225 turnip: add support for VK_KHR_global_priority
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
2022-09-14 01:38:54 +00:00
Chia-I Wu
6aa06b1b9f turnip: add tu_physical_device::submitqueue_priority_count
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
2022-09-14 01:38:54 +00:00
Chia-I Wu
79c75a3e97 turnip: fix error handling for tu_queue_init
tu_queue_finish can only be called on initialized queues.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
2022-09-14 01:38:54 +00:00
Ruijing Dong
0308abbe46 frontends/va: add HRD, filler data enable and etc
HRD parameters and filler data enable and skip frame
enable data are needed even though some application
doesn't use them.

Also for per picture rate control, max_qp and min_qp
are added.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
2022-09-14 00:16:20 +00:00
Ruijing Dong
3c8937d363 frontends/va: add max_frame_size into rate control
why:
max au size and per picture rate control data structure
need to follow the input

how:
have max_frame_size as the input to rate control
also re-calculate other rate control related params

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
2022-09-14 00:16:20 +00:00
Ruijing Dong
6646ae2576 frontends/va: change getEncParamPreset location
why:
getEncParamPreset functions overwrite the incoming
messages.

how:
To change a location after the decoder is created,
so that if no incoming message the default ones
will be used otherwise the new messages will
overwrite the default values.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
2022-09-14 00:16:20 +00:00
Ruijing Dong
72fffa62d5 frontend/va: remove some unnecessary code
clean up some code related to h264 encoding.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
2022-09-14 00:16:19 +00:00
Chia-I Wu
2f4532e2d1 subprojects: uprev perfetto to v29.0
This is mainly to get perfetto's commit 3e7228376 ("tracing: Clean up
platform TLS state on shutdown").

Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Sami Kyöstilä <skyostil@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18502>
2022-09-14 00:07:54 +00:00
Chia-I Wu
3c76091801 vulkan: update ALLOWED_ANDROID_VERSION for api level 33
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18476>
2022-09-13 23:34:58 +00:00
Yiwei Zhang
e9b995ecf4 venus: ignore pInheritanceInfo if not secondary command buffer
TEST: no segfault in dEQP-VK.api.command_buffers.bad_inheritance_info_random

Fixes: 6f5289df53 ("venus: refactor VkCommandBufferBeginInfo fixups to function")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18583>
2022-09-13 23:19:54 +00:00
Emma Anholt
d862a2ebcb turnip: Only emit descriptor loads for active stages in the pipeline.
zink has a push descriptor template layout that has every possible stage,
which gets used regardless of what stages are in the pipeline.  By
skipping over the unused stages, we cut the CP overhead.

Improves TU_DEBUG=sysmem gfxbench gl_driver2 on zink by 6.57% +/-
0.331143% (n=5).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>
2022-09-13 22:19:43 +00:00
Emma Anholt
f51bbcc8ae ci/turnip: Add missing a618 full-run bypass fails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>
2022-09-13 22:19:43 +00:00
Adam Jackson
ed2e3f5871 wsi/x11: Fix the is-visual-supported check
This was sort of well intentioned, but wrong. bits_per_rgb_value is the
number of significant bits in the color (channel) specification, not the
number of bits used to name that color within the pixel. If you have a
depth 24 visual but the colormap is 11 bits deep then each of those
channels selects one of 256 11-bit color values in the output ramp.

The open source drivers mostly don't expose anything like that, but
nvidia does, and we refuse to work. That's silly. Practically speaking
we can probably render to any TrueColor or DirectColor visual that your
X server exposes, since it is probably not going to have visuals for
non-color-renderable formats. Just check the visual class instead.

Likewise when matching formats to visuals, count the bits in the rgb
masks in the visual.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6995
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18381>
2022-09-13 21:52:55 +00:00
Rhys Perry
c23411a970 nir/algebraic: optimize bits=umin(bits, 32-(offset&0x1f))
Optimizes patterns which are created by recent versions of vkd3d-proton,
when constant folding doesn't eliminate it entirely:
- ubitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- ibitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- bitfield_insert(base, insert, offset, umin(bits, 32-(offset&0x1f)))

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13225>
2022-09-13 20:36:06 +00:00