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intel/genxml: add VFG_PREEMPTION_CHICKEN_BITS register

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This can be used to disable batch preemption on DG2+ either
completely or with selected primitive topologies.

Commit adds bit explicitly for Polygon, Trifan and LineLoop
topologies for Wa_14015207028.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18456>
This commit is contained in:
Tapani Pälli 2022-05-11 12:54:41 +03:00 • committed by Marge Bot
parent 5bfca00d31
commit d5d4604aa6
1 changed files with 7 additions and 0 deletions
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7
src/intel/genxml/gen125.xml
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@ -8086,6 +8086,13 @@
<field name="GAC Done" start="31" end="31" type="bool"/>
</register>
<register name="VFG_PREEMPTION_CHICKEN_BITS" length="1" num="0x83B4">
<field name="Batch Preemption Disable" start="8" end="8" type="bool"/>
<field name="PolygonTrifanLineLoop Preemption Disable" start="4" end="4" type="bool"/>
<field name="Batch Preemption Disable Mask" start="24" end="24" type="bool"/>
<field name="PolygonTrifanLineLoop Preemption Disable Mask" start="20" end="20" type="bool"/>
</register>
<register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
<field name="VS Invocation Count Report" start="0" end="63" type="uint"/>
</register>