It's very common needing to extract or overwrite a certain field
in an already packed register value, so add macros to do that
instead of manually doing that each time.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35088>
Now that we're no longer using multiple artifacts, we can drop the
LAVA_ prefix from the S3_ARTIFACT_NAME variable name for simplicity.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34980>
Compared to the existing Debian-based x86_64_pyutils container, this
Alpine-based variant reduces the image size by approximately 83%.
Include all the necessary python artifacts, including lava_job_submitter
in the container to avoid having to download them at the start of each
test job.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34980>
When using shader overrides, the assembler will be called a 2nd time
which will try to dereference the freed constant_data. Fix this by not
explicitly freeing constant_data, it's ralloc'd in the context of the
shader variant anyway so will be freed automatically.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35128>
Firmware packages continue to grow in size, so stop installing them in
the test-base image.
The necessary firmware is now collected and uploaded per vendor in an
external repository.
LAVA devices can opt into optional firmware by specifying the name of the
archive via LAVA_FIRMWARE.
For bare-metal, Qualcomm firmware required for DUTs in the Google lab is
included in the baremetal image.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13051
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34861>
The cheza DUTs are retired and no longer active.
The pre-merge jobs have already been disabled, do the same for the
nightly ones as well.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35018>
As previously documented, this mode either uses LRZ or early-z
(when LRZ is invalid).
Though it has some limitations, it's not compatible with:
- Lack of D/S attachment
- Stencil writes on stencil or depth test failure
- Per-sample shading
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34973>
It was accidentally made sticky when LRZ is disabled. That resulted
in a big perf regression in some games.
Fixes: 847ad80e03 ("tu/lrz: Consider FS depth layout when gl_FragDepth is written")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35029>
This saves a bit of bandwidth when we're not going to use the value.
Improves renderpass times across 4 affected traces I tested (bioshock,
stranded deep, transport fever, and godot material testers) on sysmem by
.3% +/- .1%.
A similar change for avoiding stencil reads showed no change on the one
app affected among all of our renderdoc traces, so that's left out.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34964>
With EARLY_Z depth is written before FS is executed, so if FS writes
gl_SampleMask - the d/s written before FS would be incorrect since
sample mask can kill samples. However, if there is no d/s write
it's ok to kill fragment before FS.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34900>
Switch to using the newly available ir3_legalize_state API in
ir3_postsched. This has a few advantages:
- Prevents duplication of delay/sync logic. ir3_postsched is currently
missing a lot of the complexities implemented in ir3_legalize. Reusing
the logic makes sure ir3_postsched is kept up to date with these
complexities.
- Allows ir3_postsched to have a global view (i.e., across blocks) on
delay and sync state. Currently, all information is cleared at the
start of blocks which makes us underestimate required delays.
- Allows ir3_postsched to have a more accurate view on required sync
flags. We currently calculate requirement once based on whether an
instruction's sources come from a ss/sy-producer. This does not take
into account whether sources have already been synced. Now we can do
this.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
sync_update currently only deals with the current instruction but there
are a few cases where syncs depend on the previous instruction (e.g.,
barriers). Add those to sync_update/ir3_required_sync_flags to have all
the sync logic centralized.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
Now that we have the block's final cycle value available in its state,
we don't have to subtract it at the end of a block anymore, but we can
do it at the beginning when merging it into its successor state. This
will save us one iteration over all its ready slots.
Signed-off-by: Job Noorman <job@noorman.info>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
Having the cycle as part of the state will become convenient for two
reasons:
- It will allow us to merge the state of predecessors without having to
normalize states at the end of blocks (i.e., we now have to subtract
the block's final cycle value from its ready slots at the end of the
block; having its final cycle value available in its state will allow
us to do this when merging predecessor states at the start of the
block).
- We can update the cycle value as part of delay/sync state update
routines. This way, the user doesn't have to worry about which
instructions should actually update the cycle as this logic is nicely
encapsulated.
This is part of the preparation for making the delay/sync legalization
logic available outside of ir3_legalize.
Signed-off-by: Job Noorman <job@noorman.info>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
Resetting the ss/sy delays at the start of blocks would underestimate
the actual delays at runtime. Make the estimate more accurate by keeping
track of outstanding delays at the end of blocks and setting the initial
delays of blocks to the maximum of their predecessor blocks.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
The `asmroundtrip` IR3_SHADER_DEBUG option enables roundtrip testing of
ir3 asm facilities by generating disassembly for each compiled shader
variant, parsing that disassembly back into ir3 and assembling back into
binary, with the expectation that the initial binary and the post-roundtrip
binary are identical.
This should give some guarantee that any shader that ir3 can produce can
also be constructed through assembly and fed back into ir3.
When enabled, each shader variant has a parallel roundtrip variant created.
At the moment this variant is discarded after validation, but it could
replace the initial variant in the future to also test behavior of such
roundtrip-generated binary and accompanying metadata.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34076>
Adjust ir3 parsing rules for texture prefetches to the current state. Those
rules expect the write mask to always be present, so the disassembly
production code is adjusted accordingly.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34076>
For dp2acc and dp4acc, don't display the derived NOP value by default, but
do display repeat flags for source registers. When the nop encoding
condition is met, the derived NOP value should be shown, mirroring what the
base cat3 instruction specification does.
Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34076>
