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ir3/legalize: extract sync_update helper
We will want to use this functionality in ir3_postsched. Signed-off-by: Job Noorman <job@noorman.info> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
This commit is contained in:
Job Noorman
Marge Bot
parent
b91828d553
commit
ee430745fe
1 changed files with 104 additions and 89 deletions
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@ -232,6 +232,105 @@ apply_sy(struct ir3_instruction *instr,
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state->needs_sy_for_const = false;
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}
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static void
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sync_update(struct ir3_legalize_state *state, struct ir3_compiler *compiler,
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struct ir3_instruction *n)
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{
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bool n_is_scalar_alu = is_scalar_alu(n, compiler);
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if (is_sfu(n) || n->opc == OPC_SHFL)
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regmask_set(&state->needs_ss, n->dsts[0]);
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foreach_dst (dst, n) {
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if (dst->flags & IR3_REG_SHARED) {
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if (n_is_scalar_alu) {
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if (dst->flags & IR3_REG_HALF)
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regmask_set(&state->needs_ss_scalar_full, dst);
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else
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regmask_set(&state->needs_ss_scalar_half, dst);
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} else {
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regmask_set(&state->needs_ss, dst);
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}
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} else if (reg_is_addr1(dst) && n->block->in_early_preamble) {
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regmask_set(&state->needs_ss, dst);
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}
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}
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if (is_tex_or_prefetch(n) && n->dsts_count > 0) {
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else if (n->opc == OPC_RESINFO && n->dsts_count > 0) {
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regmask_set(&state->needs_ss, n->dsts[0]);
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} else if (is_load(n)) {
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if (is_local_mem_load(n))
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regmask_set(&state->needs_ss, n->dsts[0]);
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else
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else if (is_atomic(n->opc)) {
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if (is_bindless_atomic(n->opc)) {
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regmask_set(&state->needs_sy, n->srcs[2]);
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} else if (is_global_a3xx_atomic(n->opc) ||
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is_global_a6xx_atomic(n->opc)) {
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else {
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regmask_set(&state->needs_ss, n->dsts[0]);
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}
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} else if (n->opc == OPC_PUSH_CONSTS_LOAD_MACRO || n->opc == OPC_STC) {
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state->needs_ss_for_const = true;
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} else if (n->opc == OPC_LDC_K) {
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state->needs_sy_for_const = true;
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}
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/* both tex/sfu appear to not always immediately consume
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* their src register(s):
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*/
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if (is_war_hazard_producer(n)) {
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/* These WAR hazards can always be resolved with (ss). However, when
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* the reader is a sy-producer, they can also be resolved using (sy)
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* because once we have synced the reader's results using (sy), its
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* sources have definitely been consumed. We track the two cases
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* separately so that we don't add an unnecessary (ss) if a (sy) sync
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* already happened.
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* For example, this prevents adding the unnecessary (ss) in the
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* following sequence:
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* sam rd, rs, ...
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* (sy)... ; sam synced so consumed its sources
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* (ss)write rs ; (ss) unnecessary since rs has been consumed already
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*/
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bool needs_ss = is_ss_producer(n) || is_store(n) || n->opc == OPC_STC;
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/* It seems like ray_intersection WAR hazards cannot be resolved using
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* (ss) and need a (sy) sync instead.
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*/
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bool needs_sy = n->opc == OPC_RAY_INTERSECTION;
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if (n_is_scalar_alu) {
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/* Scalar ALU also does not immediately read its source because it
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* is not executed right away, but scalar ALU instructions are
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* executed in-order so subsequent scalar ALU instructions don't
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* need to wait for previous ones.
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*/
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regmask_t *mask = needs_ss ? &state->needs_ss_scalar_war
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: &state->needs_ss_or_sy_scalar_war;
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foreach_src (reg, n) {
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if ((reg->flags & IR3_REG_SHARED) || is_reg_a0(reg)) {
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regmask_set(mask, reg);
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}
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}
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} else {
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regmask_t *mask = needs_sy ? &state->needs_sy_war
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: needs_ss ? &state->needs_ss_war
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: &state->needs_ss_or_sy_war;
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foreach_src (reg, n) {
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if (!(reg->flags & (IR3_REG_IMMED | IR3_REG_CONST))) {
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regmask_set(mask, reg);
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}
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}
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}
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}
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}
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static bool
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count_instruction(struct ir3_instruction *n, struct ir3_compiler *compiler)
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{
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@ -646,106 +745,22 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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list_addtail(&n->node, &block->instr_list);
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}
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if (is_sfu(n) || n->opc == OPC_SHFL)
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regmask_set(&state->needs_ss, n->dsts[0]);
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sync_update(state, ctx->compiler, n);
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foreach_dst (dst, n) {
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if (dst->flags & IR3_REG_SHARED) {
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if (n_is_scalar_alu) {
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if (dst->flags & IR3_REG_HALF)
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regmask_set(&state->needs_ss_scalar_full, dst);
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else
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regmask_set(&state->needs_ss_scalar_half, dst);
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} else {
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regmask_set(&state->needs_ss, dst);
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}
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} else if (reg_is_addr1(dst) && block->in_early_preamble) {
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regmask_set(&state->needs_ss, dst);
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}
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if (n->opc == OPC_META_TEX_PREFETCH) {
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assert(n->dsts_count > 0);
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ctx->has_tex_prefetch = true;
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}
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if (is_tex_or_prefetch(n) && n->dsts_count > 0) {
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regmask_set(&state->needs_sy, n->dsts[0]);
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if (n->opc == OPC_META_TEX_PREFETCH)
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ctx->has_tex_prefetch = true;
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} else if (n->opc == OPC_RESINFO && n->dsts_count > 0) {
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regmask_set(&state->needs_ss, n->dsts[0]);
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if (n->opc == OPC_RESINFO && n->dsts_count > 0) {
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ir3_NOP(&build)->flags |= IR3_INSTR_SS;
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last_input_needs_ss = false;
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} else if (is_load(n)) {
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if (is_local_mem_load(n))
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regmask_set(&state->needs_ss, n->dsts[0]);
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else
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else if (is_atomic(n->opc)) {
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if (is_bindless_atomic(n->opc)) {
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regmask_set(&state->needs_sy, n->srcs[2]);
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} else if (is_global_a3xx_atomic(n->opc) ||
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is_global_a6xx_atomic(n->opc)) {
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regmask_set(&state->needs_sy, n->dsts[0]);
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} else {
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regmask_set(&state->needs_ss, n->dsts[0]);
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}
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} else if (n->opc == OPC_PUSH_CONSTS_LOAD_MACRO || n->opc == OPC_STC) {
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state->needs_ss_for_const = true;
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} else if (n->opc == OPC_LDC_K) {
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state->needs_sy_for_const = true;
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}
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if (is_ssbo(n->opc) || is_global_a3xx_atomic(n->opc) ||
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is_bindless_atomic(n->opc))
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ctx->so->has_ssbo = true;
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/* both tex/sfu appear to not always immediately consume
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* their src register(s):
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*/
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if (is_war_hazard_producer(n)) {
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/* These WAR hazards can always be resolved with (ss). However, when
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* the reader is a sy-producer, they can also be resolved using (sy)
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* because once we have synced the reader's results using (sy), its
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* sources have definitely been consumed. We track the two cases
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* separately so that we don't add an unnecessary (ss) if a (sy) sync
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* already happened.
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* For example, this prevents adding the unnecessary (ss) in the
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* following sequence:
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* sam rd, rs, ...
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* (sy)... ; sam synced so consumed its sources
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* (ss)write rs ; (ss) unnecessary since rs has been consumed already
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*/
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bool needs_ss = is_ss_producer(n) || is_store(n) || n->opc == OPC_STC;
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/* It seems like ray_intersection WAR hazards cannot be resolved using
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* (ss) and need a (sy) sync instead.
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*/
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bool needs_sy = n->opc == OPC_RAY_INTERSECTION;
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if (n_is_scalar_alu) {
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/* Scalar ALU also does not immediately read its source because it
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* is not executed right away, but scalar ALU instructions are
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* executed in-order so subsequent scalar ALU instructions don't
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* need to wait for previous ones.
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*/
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regmask_t *mask = needs_ss ? &state->needs_ss_scalar_war
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: &state->needs_ss_or_sy_scalar_war;
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foreach_src (reg, n) {
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if ((reg->flags & IR3_REG_SHARED) || is_reg_a0(reg)) {
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regmask_set(mask, reg);
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}
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}
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} else {
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regmask_t *mask = needs_sy ? &state->needs_sy_war
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: needs_ss ? &state->needs_ss_war
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: &state->needs_ss_or_sy_war;
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foreach_src (reg, n) {
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if (!(reg->flags & (IR3_REG_IMMED | IR3_REG_CONST))) {
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regmask_set(mask, reg);
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}
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}
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}
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}
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bool count = count_instruction(n, ctx->compiler);
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if (count)
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state->cycle += 1;
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