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ir3/legalize: extract ir3_required_sync_flags helper
We will want to use this functionality in ir3_postsched. Signed-off-by: Job Noorman <job@noorman.info> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34108>
This commit is contained in:
Job Noorman
Marge Bot
parent
540cee6c3b
commit
b91828d553
1 changed files with 103 additions and 82 deletions
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@ -87,18 +87,22 @@ struct ir3_legalize_block_data {
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static inline bool
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needs_ss_war(struct ir3_legalize_state *state, struct ir3_register *dst,
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bool is_scalar_alu)
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bool is_scalar_alu, enum ir3_instruction_flags cur_flags)
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{
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if (regmask_get(&state->needs_ss_war, dst))
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return true;
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if (regmask_get(&state->needs_ss_or_sy_war, dst))
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if (!(cur_flags & IR3_INSTR_SY) &&
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regmask_get(&state->needs_ss_or_sy_war, dst)) {
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return true;
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}
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if (!is_scalar_alu) {
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if (regmask_get(&state->needs_ss_scalar_war, dst))
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return true;
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if (regmask_get(&state->needs_ss_or_sy_scalar_war, dst))
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if (!(cur_flags & IR3_INSTR_SY) &&
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regmask_get(&state->needs_ss_or_sy_scalar_war, dst)) {
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return true;
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}
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}
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return false;
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@ -110,6 +114,95 @@ needs_sy_war(struct ir3_legalize_state *state, struct ir3_register *dst)
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return regmask_get(&state->needs_sy_war, dst);
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}
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static enum ir3_instruction_flags
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ir3_required_sync_flags(struct ir3_legalize_state *state,
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struct ir3_compiler *compiler,
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struct ir3_instruction *n)
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{
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enum ir3_instruction_flags flags = 0;
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bool n_is_scalar_alu = is_scalar_alu(n, compiler);
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/* NOTE: consider dst register too.. it could happen that
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* texture sample instruction (for example) writes some
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* components which are unused. A subsequent instruction
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* that writes the same register can race w/ the sam instr
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* resulting in undefined results:
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*/
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for (unsigned i = 0; i < n->dsts_count + n->srcs_count; i++) {
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struct ir3_register *reg;
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if (i < n->dsts_count)
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reg = n->dsts[i];
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else
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reg = n->srcs[i - n->dsts_count];
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if (is_reg_gpr(reg)) {
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/* TODO: we probably only need (ss) for alu
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* instr consuming sfu result.. need to make
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* some tests for both this and (sy)..
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*/
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if (regmask_get(&state->needs_ss, reg)) {
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flags |= IR3_INSTR_SS;
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}
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/* There is a fast feedback path for scalar ALU instructions which
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* only takes 1 cycle of latency, similar to the normal 3 cycle
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* latency path for ALU instructions. For this fast path the
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* producer and consumer must use the same register size (i.e. no
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* writing a full register and then reading half of it or vice
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* versa). If we don't hit this path, either because of a mismatched
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* size or a read via the regular ALU, then the write latency is
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* variable and we must use (ss) to wait for the scalar ALU. This is
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* different from the fixed 6 cycle latency for mismatched vector
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* ALU accesses.
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*/
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if (n_is_scalar_alu) {
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/* Check if we have a mismatched size RaW dependency */
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if (regmask_get((reg->flags & IR3_REG_HALF)
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? &state->needs_ss_scalar_half
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: &state->needs_ss_scalar_full,
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reg)) {
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flags |= IR3_INSTR_SS;
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}
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} else {
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/* check if we have a scalar -> vector RaW dependency */
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if (regmask_get(&state->needs_ss_scalar_half, reg) ||
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regmask_get(&state->needs_ss_scalar_full, reg)) {
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flags |= IR3_INSTR_SS;
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}
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}
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if (regmask_get(&state->needs_sy, reg)) {
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flags |= IR3_INSTR_SY;
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}
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} else if ((reg->flags & IR3_REG_CONST)) {
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if (state->needs_ss_for_const) {
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flags |= IR3_INSTR_SS;
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}
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if (state->needs_sy_for_const) {
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flags |= IR3_INSTR_SY;
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}
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} else if (reg_is_addr1(reg) && n->block->in_early_preamble) {
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if (regmask_get(&state->needs_ss, reg)) {
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flags |= IR3_INSTR_SS;
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}
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}
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}
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foreach_dst (reg, n) {
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if (reg->flags & IR3_REG_RT)
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continue;
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if (needs_sy_war(state, reg)) {
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flags |= IR3_INSTR_SY;
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}
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if (needs_ss_war(state, reg, n_is_scalar_alu, flags)) {
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flags |= IR3_INSTR_SS;
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}
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}
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return flags;
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}
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static inline void
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apply_ss(struct ir3_instruction *instr,
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struct ir3_legalize_state *state,
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@ -472,87 +565,15 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
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bool n_is_scalar_alu = is_scalar_alu(n, ctx->compiler);
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/* NOTE: consider dst register too.. it could happen that
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* texture sample instruction (for example) writes some
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* components which are unused. A subsequent instruction
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* that writes the same register can race w/ the sam instr
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* resulting in undefined results:
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*/
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for (i = 0; i < n->dsts_count + n->srcs_count; i++) {
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struct ir3_register *reg;
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if (i < n->dsts_count)
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reg = n->dsts[i];
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else
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reg = n->srcs[i - n->dsts_count];
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enum ir3_instruction_flags sync_flags =
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ir3_required_sync_flags(state, ctx->compiler, n);
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if (is_reg_gpr(reg)) {
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/* TODO: we probably only need (ss) for alu
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* instr consuming sfu result.. need to make
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* some tests for both this and (sy)..
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*/
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if (regmask_get(&state->needs_ss, reg)) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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/* There is a fast feedback path for scalar ALU instructions which
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* only takes 1 cycle of latency, similar to the normal 3 cycle
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* latency path for ALU instructions. For this fast path the
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* producer and consumer must use the same register size (i.e. no
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* writing a full register and then reading half of it or vice
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* versa). If we don't hit this path, either because of a mismatched
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* size or a read via the regular ALU, then the write latency is
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* variable and we must use (ss) to wait for the scalar ALU. This is
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* different from the fixed 6 cycle latency for mismatched vector
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* ALU accesses.
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*/
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if (n_is_scalar_alu) {
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/* Check if we have a mismatched size RaW dependency */
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if (regmask_get((reg->flags & IR3_REG_HALF) ?
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&state->needs_ss_scalar_half :
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&state->needs_ss_scalar_full, reg)) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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} else {
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/* check if we have a scalar -> vector RaW dependency */
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if (regmask_get(&state->needs_ss_scalar_half, reg) ||
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regmask_get(&state->needs_ss_scalar_full, reg)) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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}
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if (regmask_get(&state->needs_sy, reg)) {
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apply_sy(n, state, mergedregs);
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}
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} else if ((reg->flags & IR3_REG_CONST)) {
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if (state->needs_ss_for_const) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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if (state->needs_sy_for_const) {
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apply_sy(n, state, mergedregs);
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}
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} else if (reg_is_addr1(reg) && block->in_early_preamble) {
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if (regmask_get(&state->needs_ss, reg)) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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}
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if (sync_flags & IR3_INSTR_SS) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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foreach_dst (reg, n) {
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if (reg->flags & IR3_REG_RT)
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continue;
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if (needs_sy_war(state, reg)) {
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apply_sy(n, state, mergedregs);
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}
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if (needs_ss_war(state, reg, n_is_scalar_alu)) {
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apply_ss(n, state, mergedregs);
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last_input_needs_ss = false;
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}
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if (sync_flags & IR3_INSTR_SY) {
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apply_sy(n, state, mergedregs);
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}
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/* I'm not exactly what this is for, but it seems we need this on every
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