freedreno,tu: Read and pass to compiler uche_trap_base

KGSL always exposed uche_trap_base, and MSM only recently
got support for it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29860>

src/freedreno/drm/freedreno_drmif.h

@@ -47,6 +47,7 @@ enum fd_param_id {
    FD_SUSPEND_COUNT, /* # of times the GPU has suspended, and potentially lost state */
    FD_SYSPROF,       /* Settable (for CAP_SYS_ADMIN) param for system profiling */
    FD_VA_SIZE,       /* GPU virtual address size */
+   FD_UCHE_TRAP_BASE,
 };
 
 /**

src/freedreno/drm/msm/msm_pipe.c

@@ -84,6 +84,8 @@ msm_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param,
       return query_param(pipe, MSM_PARAM_SUSPENDS, value);
    case FD_VA_SIZE:
       return query_param(pipe, MSM_PARAM_VA_SIZE, value);
+   case FD_UCHE_TRAP_BASE:
+      return query_param(pipe, MSM_PARAM_UCHE_TRAP_BASE, value);
    default:
       ERROR_MSG("invalid param id: %d", param);
       return -1;

src/freedreno/drm/virtio/virtio_pipe.c

@@ -88,6 +88,8 @@ virtio_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param,
    case FD_VA_SIZE:
       *value = virtio_dev->vdrm->caps.u.msm.va_size;
       return 0;
+   case FD_UCHE_TRAP_BASE:
+      return query_param(pipe, MSM_PARAM_UCHE_TRAP_BASE, value);
    default:
       ERROR_MSG("invalid param id: %d", param);
       return -1;

src/freedreno/ir3/ir3_compiler.h

@@ -54,6 +54,8 @@ struct ir3_compiler_options {
 
    /* "dual_color_blend_by_location" workaround is enabled: */
    bool dual_color_blend_by_location;
+
+   uint64_t uche_trap_base;
 };
 
 struct ir3_compiler {

src/freedreno/ir3/ir3_disk_cache.c

@@ -36,13 +36,22 @@ ir3_disk_cache_init(struct ir3_compiler *compiler)
    const char *renderer = fd_dev_name(compiler->dev_id);
    const struct build_id_note *note =
       build_id_find_nhdr_for_addr(ir3_disk_cache_init);
-   assert(note && build_id_length(note) == 20); /* sha1 */
+   unsigned build_id_len = build_id_length(note);
+   assert(note && build_id_len == 20); /* sha1 */
 
    const uint8_t *id_sha1 = build_id_data(note);
    assert(id_sha1);
 
+   struct mesa_sha1 ctx;
+   uint8_t sha1[SHA1_DIGEST_LENGTH];
+   _mesa_sha1_init(&ctx);
+   _mesa_sha1_update(&ctx, id_sha1, build_id_len);
+   _mesa_sha1_update(&ctx, &compiler->options.uche_trap_base,
+                     sizeof(compiler->options.uche_trap_base));
+   _mesa_sha1_final(&ctx, sha1);
+
    char timestamp[41];
-   _mesa_sha1_format(timestamp, id_sha1);
+   _mesa_sha1_format(timestamp, sha1);
 
    uint64_t driver_flags = ir3_shader_debug_hash_key();
    compiler->disk_cache = disk_cache_create(renderer, timestamp, driver_flags);

src/freedreno/vulkan/tu_device.cc

@@ -72,6 +72,7 @@ tu_device_get_cache_uuid(struct tu_physical_device *device, void *uuid)
 
    _mesa_sha1_update(&ctx, &family, sizeof(family));
    _mesa_sha1_update(&ctx, &driver_flags, sizeof(driver_flags));
+   _mesa_sha1_update(&ctx, &device->uche_trap_base, sizeof(device->uche_trap_base));
    _mesa_sha1_final(&ctx, sha1);
 
    memcpy(uuid, sha1, VK_UUID_SIZE);
@@ -2588,6 +2589,7 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
          .storage_16bit = physical_device->info->a6xx.storage_16bit,
          .storage_8bit = physical_device->info->a7xx.storage_8bit,
          .shared_push_consts = !TU_DEBUG(PUSH_CONSTS_PER_STAGE),
+         .uche_trap_base = physical_device->uche_trap_base,
       };
       device->compiler = ir3_compiler_create(
          NULL, &physical_device->dev_id, physical_device->info, &ir3_options);

src/freedreno/vulkan/tu_device.h

@@ -114,6 +114,8 @@ struct tu_physical_device
    uint32_t vpc_attr_buf_offset_bypass;
    uint32_t vpc_attr_buf_size_bypass;
 
+   uint64_t uche_trap_base;
+
    /* Amount of usable descriptor sets, this excludes any reserved set */
    uint32_t usable_sets;
    /* Index of the reserved descriptor set, may be -1 if unset */

src/freedreno/vulkan/tu_knl_drm_msm.cc

@@ -169,6 +169,17 @@ tu_drm_get_ubwc_swizzle(const struct tu_physical_device *dev)
    return value;
 }
 
+static uint64_t
+tu_drm_get_uche_trap_base(const struct tu_physical_device *dev)
+{
+   uint64_t value;
+   int ret = tu_drm_get_param(dev->local_fd, MSM_PARAM_UCHE_TRAP_BASE, &value);
+   if (ret)
+      return 0x1fffffffff000ull;
+
+   return value;
+}
+
 static bool
 tu_drm_is_memory_type_supported(int fd, uint32_t flags)
 {
@@ -1065,6 +1076,8 @@ tu_knl_drm_msm_load(struct tu_instance *instance,
    device->ubwc_config.bank_swizzle_levels = tu_drm_get_ubwc_swizzle(device);
    device->ubwc_config.macrotile_mode = tu_drm_get_macrotile_mode(device);
 
+   device->uche_trap_base = tu_drm_get_uche_trap_base(device);
+
    device->syncobj_type = vk_drm_syncobj_get_type(fd);
    /* we don't support DRM_CAP_SYNCOBJ_TIMELINE, but drm-shim does */
    if (!(device->syncobj_type.features & VK_SYNC_FEATURE_TIMELINE))

src/freedreno/vulkan/tu_knl_drm_virtio.cc

@@ -288,6 +288,17 @@ tu_drm_get_ubwc_swizzle(struct vdrm_device *vdrm)
    return value;
 }
 
+static uint64_t
+tu_drm_get_uche_trap_base(struct vdrm_device *vdrm)
+{
+   uint64_t value;
+   int ret = tu_drm_get_param(vdrm, MSM_PARAM_UCHE_TRAP_BASE, &value);
+   if (ret)
+      return 0x1fffffffff000ull;
+
+   return value;
+}
+
 static int
 virtio_device_get_gpu_timestamp(struct tu_device *dev, uint64_t *ts)
 {
@@ -1167,6 +1178,7 @@ tu_knl_drm_virtio_load(struct tu_instance *instance,
 
    uint32_t bank_swizzle_levels = tu_drm_get_ubwc_swizzle(vdrm);
    enum fdl_macrotile_mode macrotile_mode = tu_drm_get_macrotile_mode(vdrm);
+   uint64_t uche_trap_base = tu_drm_get_uche_trap_base(vdrm);
 
    bool has_raytracing = tu_drm_get_raytracing(vdrm);
 
@@ -1233,6 +1245,7 @@ tu_knl_drm_virtio_load(struct tu_instance *instance,
    device->ubwc_config.highest_bank_bit = caps.u.msm.highest_bank_bit;
    device->has_set_iova   = true;
    device->has_preemption = has_preemption;
+   device->uche_trap_base = uche_trap_base;
 
    device->ubwc_config.bank_swizzle_levels = bank_swizzle_levels;
    device->ubwc_config.macrotile_mode = macrotile_mode;

src/freedreno/vulkan/tu_knl_kgsl.cc

@@ -1485,6 +1485,11 @@ tu_knl_kgsl_load(struct tu_instance *instance, int fd)
                      sizeof(ubwc_version)))
       goto fail;
 
+   if (get_kgsl_prop(fd, KGSL_PROP_UCHE_TRAP_BASE, &device->uche_trap_base,
+                     sizeof(device->uche_trap_base))) {
+      /* It is known to be hardcoded to */
+      device->uche_trap_base = 0x1fffffffff000ull;
+   }
 
    /* kgsl version check? */
 

src/gallium/drivers/freedreno/freedreno_screen.c

@@ -923,6 +923,9 @@ fd_screen_create(int fd,
    if (fd_device_version(dev) >= FD_VERSION_ROBUSTNESS)
       screen->has_robustness = true;
 
+   if (fd_pipe_get_param(screen->pipe, FD_UCHE_TRAP_BASE, &val))
+      screen->uche_trap_base = screen->gen >= 6 ? 0x1fffffffff000ull : 0ull;
+
    screen->has_syncobj = fd_has_syncobj(screen->dev);
 
    /* parse driconf configuration now for device specific overrides: */

src/gallium/drivers/freedreno/freedreno_screen.h

@@ -67,6 +67,8 @@ struct fd_screen {
    uint64_t gmem_base;
    uint32_t gmemsize_bytes;
 
+   uint64_t uche_trap_base;
+
    const struct fd_dev_id *dev_id;
    uint8_t gen;      /* GPU (major) generation */
    uint32_t gpu_id;  /* 220, 305, etc */

src/gallium/drivers/freedreno/ir3/ir3_gallium.c

@@ -560,6 +560,7 @@ ir3_screen_init(struct pipe_screen *pscreen)
       .bindless_fb_read_slot = IR3_BINDLESS_IMAGE_OFFSET +
                                IR3_BINDLESS_IMAGE_COUNT - 1 - screen->max_rts,
       .dual_color_blend_by_location = screen->driconf.dual_color_blend_by_location,
+      .uche_trap_base = screen->uche_trap_base,
    };
 
    if (screen->gen >= 6) {