fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-11 23:10:28 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

ir3: don't sync every TCS/GEOM block

Browse source 
TCS/GEOM shaders need (sy)(ss) on their first instruction but we
accidentally set it on the first instruction of every block.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34257>
This commit is contained in:
Job Noorman 2025-03-28 12:55:11 +01:00 • committed by Marge Bot
parent 3ba315f205
commit ee0ee2a317
1 changed files with 4 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -5985,12 +5985,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
* know what we might have to wait on when coming in from VS chsh.
*/
if (so->type == MESA_SHADER_TESS_CTRL || so->type == MESA_SHADER_GEOMETRY) {
foreach_block (block, &ir->block_list) {
foreach_instr (instr, &block->instr_list) {
instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
break;
}
}
struct ir3_block *first_block = ir3_start_block(ir);
struct ir3_instruction *first_instr = list_first_entry(
&first_block->instr_list, struct ir3_instruction, node);
first_instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
}
if (ctx->compiler->gen >= 7 && so->type == MESA_SHADER_COMPUTE) {