Commit graph

219639 commits

Author SHA1 Message Date
Samuel Pitoiset
bcccd49368 ac,radeonsi: move guardband computations to common code
Added a comment from Marek Olsak explaining this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40249>
2026-03-10 12:07:46 +00:00
Samuel Pitoiset
2ca7d93519 ac,radeonsi: pre-compute some raster config in ac_gpu_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40249>
2026-03-10 12:07:46 +00:00
Samuel Pitoiset
3e8e31add7 amd/drm-shim: bump version_minor to 52
Some checks are pending
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This is required to make sure that conformant_trunc_coord is correctly
enabled/disabled. Otherwise, it might be disabled on GFX11 GPUs with
drm-shim.

Bumping the minor version shouldn't have any other effects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40313>
2026-03-10 11:19:33 +00:00
Samuel Pitoiset
db905159fd amd/drm-shim: add phoenix
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40313>
2026-03-10 11:19:33 +00:00
Samuel Pitoiset
7fd114b563 amd/drm-shim: add rembrandt
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40313>
2026-03-10 11:19:33 +00:00
Valentine Burley
8b706f4c0f ci: Update kernel to pick up new network adapter
The only change in this kernel is enabling CONFIG_IGB for upcoming jobs,
with no impact on current jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 11:12:26 +01:00
Valentine Burley
2addcc1dce venus/ci: Add an Android Venus on Turnip job on a618
Add a nightly job running Cuttlefish with Venus on Turnip.

Similar to the existing Venus-on-ANV jobs, this uses Cuttlefish's
'venus_guest_angle' mode to run deqp-vk and deqp-egl with ANGLE and
Venus inside the Android guest, with Turnip on the host.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:54:03 +01:00
Valentine Burley
3d00926006 ci: Add test-android container for arm64
Introduce the arm64 counterpart of the debian/x86_64_test-android
container/rootfs.

Building Android arm64 targets is complicated by the fact that Google
only provides the Android NDK for x86_64 hosts. Because of this, the
debian/arm64_test-android setup is split into two parts:

debian/arm64_test-android-tools
Despite the name, this is a native x86_64 container used to build
ANGLE, dEQP, and deqp-runner for Android arm64 targets. The resulting
artifacts are uploaded to S3 and later consumed by the final image.

debian/arm64_test-android
This is the final arm64 container/rootfs. It downloads the previously
built tools and installs the Cuttlefish Debian package.
The Cuttlefish guest image and additional host tools are not included
in this image. It is currently only used in LAVA, where Cuttlefish
artifacts can be deployed separately and kept cached across container
rebuilds.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:54:03 +01:00
Valentine Burley
e26a8f0e76 ci/container: Prepare test-android for multi-arch support
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:54:03 +01:00
Valentine Burley
9cd5239c01 ci/container: Generalize debian/x86_64_test-android container
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:54:03 +01:00
Valentine Burley
f50a358569 ci/android: Update Cuttlefish build
The new version has the following changes:
 - Working display on WebRTC with drm_hwcomposer after Wayland dmabuf
   server fixes
 - arm64 support for Venus GPU mode
 - Updated virglrenderer to latest main, 85c9cc77 ("vkr: enable
   VK_KHR_shader_fma")
 - Improved boot times
 - New DRM native context GPU modes

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:54:01 +01:00
Valentine Burley
12277d3f75 ci/android: Disable wifi for Cuttlefish
Wifi can occasionally cause crashes on the host, and we don't need it for
graphics testing.

[  401.084158] Unable to handle kernel paging request at virtual address ff800099ff80ffb2
[  401.092309] Mem abort info:
[  401.095190]   ESR = 0x0000000096000004
[  401.099045]   EC = 0x25: DABT (current EL), IL = 32 bits
[  401.104501]   SET = 0, FnV = 0
[  401.107640]   EA = 0, S1PTW = 0
[  401.110875]   FSC = 0x04: level 0 translation fault
[  401.115885] Data abort info:
[  401.118850]   ISV = 0, ISS = 0x00000004, ISS2 = 0x00000000
[  401.124489]   CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[  401.129684]   GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[  401.135140] [ff800099ff80ffb2] address between user and kernel address ranges
[  401.142468] Internal error: Oops: 0000000096000004 [#1]  SMP
[  401.148283] Modules linked in: vhost_vsock vhost vhost_iotlb ipv6
[  401.154556] CPU: 2 UID: 0 PID: 718 Comm: Wi-Fi HwsimMsg  Tainted: G        W           6.17.3-gddf65230edb2 #1 PREEMPT

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:53:30 +01:00
Valentine Burley
60a8785bb8 ci: Strip qemu from rootfs
Cuttlefish install qemu as a dependency, but we don't use it.
Remove it to save space.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:53:30 +01:00
Valentine Burley
0478046036 venus/ci: Remove hanging timeout override for ADL and TGL jobs
New deqp-runner version prints messages more frequently.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39993>
2026-03-10 09:53:29 +01:00
Georg Lehmann
452025f75e nir: add free bits in nir_io_semantics for future use
Some checks are pending
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40299>
2026-03-10 07:46:22 +00:00
Georg Lehmann
a25f00eaed nir: merge xfb and xfb2 into one 64bit intrinsic index
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40299>
2026-03-10 07:46:22 +00:00
Georg Lehmann
4ba581887e nir: support intrinsic indicies larger than 32 bits
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40299>
2026-03-10 07:46:21 +00:00
Georg Lehmann
abfd6a4df9 nir: don't assume indicies are always 32bit when accessing them as raw data
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40299>
2026-03-10 07:46:20 +00:00
Georg Lehmann
aa831b6690 nir/opt_algebraic: skip more redundant alignment iand
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Useful for smaller/larger loads. Also there is no reason to be bitsize
specific here if we use an signed constant.

Foz-DB Navi48:
Totals from 8 (0.01% of 114655) affected shaders:
Instrs: 7629 -> 7612 (-0.22%)
CodeSize: 40772 -> 40692 (-0.20%)
Latency: 54880 -> 54944 (+0.12%)
InvThroughput: 8879 -> 8880 (+0.01%); split: -0.08%, +0.09%
VALU: 4029 -> 4027 (-0.05%); split: -0.15%, +0.10%
SALU: 1260 -> 1249 (-0.87%)

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40292>
2026-03-10 06:57:50 +00:00
Tapani Pälli
8fb5614ba0 intel/dev: implement urb handle limits for Wa_16025326720
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40300>
2026-03-10 05:44:15 +00:00
Timothy Arceri
bd42f62b0f glx: guard glx_screen frontend_screen member
Some checks are pending
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Guards workaround code with the same conditions as glx_screen`s
frontend_screen member.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Fixes: 67eeee43e0 ("driconf: add a way to override GLX_CONTEXT_RESET_ISOLATION_BIT_ARB")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15021
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40290>
2026-03-10 01:53:15 +00:00
Paulo Zanoni
85751506ab elk: don't use instr->const_index[] directly
From what I understand, use of const_index[] by the driver is
dangerous and should be avoided, as commits such as a6330ed4d0
("nir: add ACCESS to load_uniforms") may result in the indexes
changing, breaking the driver. Switch to using the parameter names in
order to make the code more future-proof.

For elk_fs_nir.cpp and elk_vec4_tes.cpp we can verify in the generated
nir_intrinsics.c that the wanted value is actually
nir_intrinsic_base().

For elk_nir.c, according to Caio Oliveira:

  "The code is checking for certain load/store via the is_input() and
   is_output() checks a few lines above. I've checked all them have
   BASE at 0."

Thanks to Ian Romanick for his guidance regarding this patch.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39438>
2026-03-10 01:03:42 +00:00
Karol Herbst
bd552b41cc nvk: skip lowering load_global_constant_bounded on turing inside lower_load_intrinsic
Some checks are pending
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Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:05 +00:00
Karol Herbst
f7ad45e5fc nak: support has_load_global_bounded on turing and newer
Totals:
CodeSize: 9401446416 -> 8663482432 (-7.85%); split: -7.85%, +0.00%
Number of GPRs: 47297665 -> 47508294 (+0.45%); split: -0.14%, +0.59%
SLM Size: 1202912 -> 1203000 (+0.01%); split: -0.09%, +0.10%
Static cycle count: 5984801035 -> 4714013561 (-21.23%); split: -21.24%, +0.00%
Spills to memory: 44482 -> 45073 (+1.33%); split: -1.68%, +3.01%
Fills from memory: 44482 -> 45073 (+1.33%); split: -1.68%, +3.01%
Spills to reg: 184822 -> 149129 (-19.31%); split: -21.54%, +2.23%
Fills from reg: 223885 -> 170692 (-23.76%); split: -25.49%, +1.73%
Max warps/SM: 50642520 -> 50564740 (-0.15%); split: +0.03%, -0.19%

Totals from 185510 (15.95% of 1163204) affected shaders:
CodeSize: 3910084048 -> 3172120064 (-18.87%); split: -18.88%, +0.01%
Number of GPRs: 10625243 -> 10835872 (+1.98%); split: -0.63%, +2.61%
SLM Size: 659568 -> 659656 (+0.01%); split: -0.17%, +0.19%
Static cycle count: 3920553863 -> 2649766389 (-32.41%); split: -32.42%, +0.01%
Spills to memory: 8498 -> 9089 (+6.95%); split: -8.81%, +15.77%
Fills from memory: 8498 -> 9089 (+6.95%); split: -8.81%, +15.77%
Spills to reg: 109049 -> 73356 (-32.73%); split: -36.51%, +3.77%
Fills from reg: 116031 -> 62838 (-45.84%); split: -49.18%, +3.34%
Max warps/SM: 6885584 -> 6807804 (-1.13%); split: +0.25%, -1.38%

This also helps significantly reduce shader compile times since it reduces
the number of basic blocks.  With DragonAge: The Veilguard, it reduces
shader compile times by around 20%.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:05 +00:00
Karol Herbst
7722bde53b nak: use ldg input predicate in nak_nir_lower_non_uniform_ldcx
Totals:
CodeSize: 9442133184 -> 9401446416 (-0.43%); split: -0.43%, +0.00%
Number of GPRs: 47300490 -> 47297665 (-0.01%); split: -0.01%, +0.00%
Static cycle count: 6120907718 -> 5984801035 (-2.22%); split: -2.22%, +0.00%
Spills to reg: 184810 -> 184822 (+0.01%); split: -0.01%, +0.02%
Fills from reg: 223860 -> 223885 (+0.01%); split: -0.01%, +0.02%
Max warps/SM: 50641540 -> 50642520 (+0.00%); split: +0.00%, -0.00%

Totals from 12079 (1.04% of 1163204) affected shaders:
CodeSize: 461892048 -> 421205280 (-8.81%); split: -8.81%, +0.00%
Number of GPRs: 1060493 -> 1057668 (-0.27%); split: -0.43%, +0.16%
Static cycle count: 922257513 -> 786150830 (-14.76%); split: -14.76%, +0.00%
Spills to reg: 14704 -> 14716 (+0.08%); split: -0.14%, +0.22%
Fills from reg: 24213 -> 24238 (+0.10%); split: -0.08%, +0.19%
Max warps/SM: 320540 -> 321520 (+0.31%); split: +0.39%, -0.08%

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:05 +00:00
Karol Herbst
9d90cbc314 nak: add input predicate to load_global_nv and OpLd
This is new in SM75 (Turing). Let's use it because it allows us to get rid
of the if/else around bound checked global loads.

There are some changes in fossils, but it seems that's mostly due to CFG
optimizations doing things a bit differently?

Totals:
CodeSize: 9442152688 -> 9442133184 (-0.00%); split: -0.00%, +0.00%
Static cycle count: 6120910991 -> 6120907718 (-0.00%); split: -0.00%, +0.00%
Spills to reg: 184789 -> 184810 (+0.01%)
Fills from reg: 223831 -> 223860 (+0.01%); split: -0.00%, +0.01%

Totals from 334 (0.03% of 1163204) affected shaders:
CodeSize: 22020752 -> 22001248 (-0.09%); split: -0.10%, +0.01%
Static cycle count: 26582978 -> 26579705 (-0.01%); split: -0.01%, +0.00%
Spills to reg: 3110 -> 3131 (+0.68%)
Fills from reg: 3401 -> 3430 (+0.85%); split: -0.03%, +0.88%

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:05 +00:00
Karol Herbst
d2bf824baf nak: replace legalize_ext_instr with explicit lowering
legalize_ext_instr wasn't doing anything besides lowering uniform sources
and panicing on a bunch of Source types.

Having a common helper looping over all sources doesn't make much sense,
because all the instructions are widly different in regards to UGPRs. The
panics will be hit while emitting the sources as well, so this helper
provided little help and wasn't flexible enough for what we need.

Furthermore some instructions like LDG also take an additional input
predicate that legalize_ext_instr can't handle.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:04 +00:00
Karol Herbst
95f19bd5eb nak: invalidate loop analysis with nak_nir_lower_load_store
We'll start to lower load_global_bounded there and that will invalidate
loop analysis, because the amount of instructions will change within a
block.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:04 +00:00
Benjamin Cheng
8f1ace0571 radv: Disable video features for some DRM modifiers
Filter out video decode/encode format features when the DRM modifier
doesn't support video operations. Along with a CTS fix, this will fix
dEQP-VK.video.formats.* on UVD/VCN1 (which do not support swizzled
input).

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40203>
2026-03-09 23:27:46 +00:00
Iván Briano
5d22f307d5 anv: don't try to fast clear D/S with multiview
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If multiview is enabled on the render pass, baseLayer and layerCount
will be 0 and 1 respectively and throw us off.
We can still fast clear if view_mask == 1, but anything else hits the
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL restriction.

Fixes: e488773b29 ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments")

Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40229>
2026-03-09 22:49:05 +00:00
Georg Lehmann
6936282bd3 nir/opt_algebraic: remove min(a, >= 1.0) before fsat
Foz-DB Navi48:
Totals from 86 (0.08% of 114655) affected shaders:
Instrs: 217553 -> 217408 (-0.07%); split: -0.07%, +0.01%
CodeSize: 1159992 -> 1159380 (-0.05%); split: -0.06%, +0.01%
Latency: 1657600 -> 1657533 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 203205 -> 203178 (-0.01%); split: -0.02%, +0.00%
SClause: 5245 -> 5244 (-0.02%)
Copies: 13726 -> 13716 (-0.07%); split: -0.14%, +0.07%
VALU: 130151 -> 130039 (-0.09%); split: -0.09%, +0.00%
SALU: 26476 -> 26474 (-0.01%); split: -0.02%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40281>
2026-03-09 21:11:25 +00:00
Georg Lehmann
108a4d4341 nir: create more fsat using range analysis
Foz-DB Navi48:
Totals from 5922 (5.17% of 114655) affected shaders:
Instrs: 5188307 -> 5184193 (-0.08%); split: -0.09%, +0.01%
CodeSize: 27852544 -> 27843252 (-0.03%); split: -0.05%, +0.01%
Latency: 28723967 -> 28714268 (-0.03%); split: -0.04%, +0.01%
InvThroughput: 4745002 -> 4742298 (-0.06%); split: -0.07%, +0.01%
VClause: 68649 -> 68650 (+0.00%)
SClause: 103932 -> 103917 (-0.01%); split: -0.02%, +0.00%
Copies: 244683 -> 244706 (+0.01%); split: -0.01%, +0.02%
PreSGPRs: 272361 -> 272362 (+0.00%); split: -0.00%, +0.00%
VALU: 3248960 -> 3245520 (-0.11%); split: -0.11%, +0.00%
SALU: 516784 -> 516796 (+0.00%); split: -0.01%, +0.01%
VOPD: 8910 -> 8895 (-0.17%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40281>
2026-03-09 21:11:25 +00:00
Sagar Ghuge
f7e3085e6a anv: Improve bvh_no_build option
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We can't guarantee that skipping the BVH build would let the BVH memory
all zero. So explicitly set it to zero when running things with
BVH_NO_BUILD option.

This will help us to narrow down isuse if it's in BVH encoding or
application shader. Leaving uninitialized blob of memory would hit
intermittent hangs and would lead us to nowhere.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40276>
2026-03-09 20:31:27 +00:00
Felix DeGrood
8ad49647f7 intel/decoder: update warning message when buildtype=release
INTEL_DEBUG=bat is no longer supported on release drivers, instead
using a stub decoder. Update stub decoder warning message to
mention this.

Signed-off-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40306>
2026-03-09 20:01:01 +00:00
Ian Romanick
ffd4497e48 brw/asm: Don't drop accumulator number in the assembler
Previously "acc1" or "acc2" would be stored as acc0.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
1ae7a82811 brw: Fix encoding of accumulator sources of 3-source instructions
Previously the accumulator was always forced to be acc0.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
6531c425a0 brw/emit: Src1 can be accumulator on Gfx12.5 and newer
v2: Add Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
c3a5b62c08 brw/validate: Perform more 3-src validation in brw_validate instead of brw_eu_emit
v2: s/Lake/Ice Lake/ in a comment. Noticed by Caio. Add a missing Xe2
Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
1f45e33072 brw/validate: Implicit read of accumulator cannot also have explicit read
v2: Add Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:38 +00:00
Ian Romanick
8a6de2d973 brw/validate: Eliminate duplicate integer multiply validation
I think two MRs must have crossed in the mail so to speak. Keep Caio's
formatting and error message, and keep my PRM quote.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:38 +00:00
Ian Romanick
64c60582b5 elk/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT
shader-db:

Broadwell
total instructions in shared programs: 18607516 -> 18607530 (<.01%)
instructions in affected programs: 2095 -> 2109 (0.67%)
helped: 0 / HURT: 8

total cycles in shared programs: 955704436 -> 955702925 (<.01%)
cycles in affected programs: 34299 -> 32788 (-4.41%)
helped: 2 / HURT: 6

All Haswell and older platforms had similar results. (Haswell shown)
total instructions in shared programs: 16989200 -> 16989201 (<.01%)
instructions in affected programs: 461 -> 462 (0.22%)
helped: 0 / HURT: 1

total cycles in shared programs: 946537070 -> 946537035 (<.01%)
cycles in affected programs: 16378 -> 16343 (-0.21%)
helped: 1 / HURT: 0

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
2026-03-09 18:41:55 +00:00
Ian Romanick
6c6c6ce054 brw/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT
This optimization was added in October 2013, and the error was only just
now discovered. Removing the SEL.G.SAT optimization affected zero
shader-db shaders, and it affected 9 fossil-db shaders for instruction
size only.

I haven't checked to see if any of the hurt shaders are helped by
!39987.

shader-db:

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17093041 -> 17093055 (<.01%)
instructions in affected programs: 2072 -> 2086 (0.68%)
helped: 0 / HURT: 8

total cycles in shared programs: 876739578 -> 876739154 (<.01%)
cycles in affected programs: 18946 -> 18522 (-2.24%)
helped: 2 / HURT: 6

fossil-db:

Lunar Lake
Totals:
Instrs: 906230557 -> 906240487 (+0.00%); split: -0.00%, +0.00%
CodeSize: 14498856128 -> 14499003168 (+0.00%); split: -0.00%, +0.00%
Send messages: 40667184 -> 40667205 (+0.00%); split: -0.00%, +0.00%
Cycle count: 104068494103 -> 104068561943 (+0.00%); split: -0.00%, +0.00%
Max live registers: 189570192 -> 189570204 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 48157648 -> 48157552 (-0.00%)
Non SSA regs after NIR: 139823587 -> 139823016 (-0.00%); split: -0.00%, +0.00%

Totals from 9172 (0.46% of 1985212) affected shaders:
Instrs: 10774709 -> 10784639 (+0.09%); split: -0.00%, +0.09%
CodeSize: 177868384 -> 178015424 (+0.08%); split: -0.08%, +0.17%
Send messages: 311154 -> 311175 (+0.01%); split: -0.00%, +0.01%
Cycle count: 232471392 -> 232539232 (+0.03%); split: -0.15%, +0.18%
Max live registers: 1243549 -> 1243561 (+0.00%); split: -0.00%, +0.01%
Max dispatch width: 196672 -> 196576 (-0.05%)
Non SSA regs after NIR: 509663 -> 509092 (-0.11%); split: -0.19%, +0.08%

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
2026-03-09 18:41:55 +00:00
Valentine Burley
827370d144 intel/ci: Document recent Intel flakes
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Not caused by the new kernel, these have been flaking for a while now.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
64b7388bc2 etnaviv/ci: Switch CI-tron to gfx-ci/linux kernel
We can now use the standard gfx-ci/linux v6.19.5 kernel for all etnaviv
jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
68e0eb78d1 freedreno/ci: Switch sm8650 to gfx-ci/linux kernel
Use the standard gfx-ci/linux v6.19.5 kernel for the a750 jobs on
sm8650-hdk.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
31090dea4c ci: Update kernel to Linux 6.19.6
The new kernel also fixes the previous issue in the virgl-traces job, but
sadly Xe regressed, so keep the 6.17 kernel in zink-anv-adl.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14161
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
efd980aa15 ci/lava: Uprev lava-job-submitter
The new version drops our internal timestamp handling since newer
gitlab-runner versions already provide native timestamp support.

It also prepares for future CI-tron support in gfx-ci/linux by appending
`noinitrd` and `initcall_blacklist=cdc_driver_init` to the kernel
cmdline, disabling the initramdisk and CDC Composite Device that CI-tron
needs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
de7a584093 radeonsi/ci: Skip subgroups.arithmetic tests on Mendocino
This is not caused by the new kernel, these tests have occasionally
timed out over the last couple of weeks.
Running them single-threaded didn't help.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Karmjit Mahil
72870051d8 zink: Fix incorrect assert checking for linear state format
With `pres->format == PIPE_FORMAT_L8_UNORM` and
`state->format == PIPE_FORMAT_L8_SRGB` the assert is triggered.
We should be comparing the linear version of `state->format` since
we're only concerned about the physical memory layout here.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31717>
2026-03-09 17:02:26 +00:00
Lionel Landwerlin
de29b88668 anv: fix pulling constant data in compute/mesh/task shaders
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Missing the accounting for the base offset.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15029
Fixes: 9f2215b480 ("anv/brw: remove push constant load emulation from the backend compiler")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40301>
2026-03-09 16:25:43 +00:00