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ac,radeonsi: pre-compute some raster config in ac_gpu_info

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40249>
This commit is contained in:
Samuel Pitoiset 2026-03-05 16:43:52 +01:00 • committed by Marge Bot
parent 3e8e31add7
commit 2ca7d93519
6 changed files with 19 additions and 19 deletions
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14
src/amd/common/ac_cmdbuf.c
View file

@ -218,23 +218,21 @@ ac_write_harvested_raster_configs(const struct radeon_info *info, struct ac_pm4_
}
static void
ac_set_raster_config(const struct radeon_info *info, struct ac_pm4_state *pm4)
ac_emit_raster_config(const struct radeon_info *info, struct ac_pm4_state *pm4)
{
const unsigned num_rb = MIN2(info->max_render_backends, 16);
const uint64_t rb_mask = info->enabled_rb_mask;
unsigned raster_config, raster_config_1;
ac_get_raster_config(info, &raster_config, &raster_config_1, NULL);
if (!rb_mask || util_bitcount64(rb_mask) >= num_rb) {
/* Always use the default config when all backends are enabled
* (or when we failed to determine the enabled backends).
*/
ac_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config);
ac_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, info->pa_sc_raster_config);
if (info->gfx_level >= GFX7)
ac_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
ac_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, info->pa_sc_raster_config_1);
} else {
ac_write_harvested_raster_configs(info, pm4, raster_config, raster_config_1);
ac_write_harvested_raster_configs(info, pm4, info->pa_sc_raster_config,
info->pa_sc_raster_config_1);
}
}
@ -301,7 +299,7 @@ gfx6_init_graphics_preamble_state(const struct ac_preamble_state *state,
}
if (info->gfx_level <= GFX8) {
ac_set_raster_config(info, pm4);
ac_emit_raster_config(info, pm4);
/* FIXME calculate these values somehow ??? */
ac_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);

7
src/amd/common/ac_gpu_info.c
View file

@ -1660,6 +1660,13 @@ ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
set_custom_cu_en_mask(info);
if (info->gfx_level >= GFX9) {
info->se_tile_repeat = 32 * info->max_se;
} else {
ac_get_raster_config(info, &info->pa_sc_raster_config,
&info->pa_sc_raster_config_1, &info->se_tile_repeat);
}
const char *ib_filename = debug_get_option("AMD_PARSE_IB", NULL);
if (ib_filename) {
FILE *f = fopen(ib_filename, "r");

5
src/amd/common/ac_gpu_info.h
View file

@ -463,6 +463,11 @@ struct radeon_info {
bool spi_cu_en_has_effect;
uint32_t spi_cu_en;
/* Raster config. */
uint32_t pa_sc_raster_config;
uint32_t pa_sc_raster_config_1;
uint32_t se_tile_repeat;
struct {
uint32_t shadow_size;
uint32_t shadow_alignment;

7
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -1334,13 +1334,6 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->ws = ws;
ws->query_info(ws, &sscreen->info);
if (sscreen->info.gfx_level >= GFX9) {
sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
} else {
ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
&sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
}
sscreen->context_roll_log_filename = debug_get_option("AMD_ROLLS", NULL);
sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0);
sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0);

3
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -510,9 +510,6 @@ struct si_screen {
uint64_t multimedia_debug_flags;
char renderer_string[183];
unsigned pa_sc_raster_config;
unsigned pa_sc_raster_config_1;
unsigned se_tile_repeat;
unsigned gs_table_depth;
unsigned eqaa_force_coverage_samples;
unsigned eqaa_force_z_samples;

2
src/gallium/drivers/radeonsi/si_state_viewport.c
View file

@ -277,7 +277,7 @@ static void si_emit_guardband(struct si_context *sctx, unsigned index)
/* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */
const unsigned hw_screen_offset_alignment =
sctx->gfx_level >= GFX11 ? 32 :
sctx->gfx_level >= GFX8 ? 16 : MAX2(sctx->screen->se_tile_repeat, 16);
sctx->gfx_level >= GFX8 ? 16 : MAX2(sctx->screen->info.se_tile_repeat, 16);
const unsigned max_hw_screen_offset = sctx->gfx_level >= GFX12 ? 32768 : 8176;
/* Indexed by quantization modes */