Since field is split in between multiple fields, we have to manually
write the values and refer to Bspec 43851 for exact values.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40733>
On Xe, we have this bit reversed. It's called Thread preemption Disable.
On Xe2+ (Bspec 56590), it's called Thread preemption with option
enabled/disabled.
AFAIK, we don't support mid-thread preemption. This patch set values
properly according to bspec.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41120>
We need to use these registers on another file and I don't want to add
another copy of their definition to our code base.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40937>
This provides bit and common code to control autostrip state.
Requirement for this is coming from Wa_14026781792. We are writing
register for Wa_14024997852 and since this register is nonmaskable
the bit needs to be written always. Helper takes care to touch only
required bits.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40344>
This doesn't have a functional impact, but when this command is run:
$ src/intel/genxml/genxml_import.py --import
It causes the gen125_rt.xml file to be processed in the expected
order, before xe2.xml.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40217>
Removes the need for emitting 3DSTATE_BINDING_TABLE_POINTER* commands
to make the HW gather push constants.
According to internal pointers, this been the default behavior on
Gfx11+.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39405>
v2: Define additional enum BLORP_OP_HIZ_PARTIAL_RESOLVE to track
partial resolves (Nanley).
v3: Add comment regarding fall back to full resolve on Gfx12.0 (Nanley).
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31139>
This optimization doesn't work when the ray query index isn't uniform across
the subgroup, which is something the spec allows. While there are some smart
ways to fix this and still avoid unnecessary spilling, its not worth investing
the time until we find a realtime raytracing workload that actually needs to
use multiple live ray queries for something.
Fixes: 1f1de7eb ("anv,brw: Allow multiple ray queries without spilling to a shadow stack")
Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39445>
Allows a shader to have multiple ray queries without spilling them to a shadow
stack. Instead, the driver provides the shader with an array of multiple
RTDispatchGlobals structs to give each query its own dedicated stack.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38778>
These registers need to be whitelisted by kernel so that we can use
it to disable autostrip at will. This is about Wa_14024997852.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37975>
Field that we currently utilize does not change place, however
there are some new fields so let's update contents to match spec.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35966>
In the C23 standard unreachable() is now a predefined function-like
macro in <stddef.h>
See https://android.googlesource.com/platform/bionic/+/HEAD/docs/c23.md#is-now-a-predefined-function_like-macro-in
And this causes build errors when building for C23:
-----------------------------------------------------------------------
In file included from ../src/util/log.h:30,
from ../src/util/log.c:30:
../src/util/macros.h:123:9: warning: "unreachable" redefined
123 | #define unreachable(str) \
| ^~~~~~~~~~~
In file included from ../src/util/macros.h:31:
/usr/lib/gcc/x86_64-linux-gnu/14/include/stddef.h:456:9: note: this is the location of the previous definition
456 | #define unreachable() (__builtin_unreachable ())
| ^~~~~~~~~~~
-----------------------------------------------------------------------
So don't redefine it with the same name, but use the name UNREACHABLE()
to also signify it's a macro.
Using a different name also makes sense because the behavior of the
macro was extending the one of __builtin_unreachable() anyway, and it
also had a different signature, accepting one argument, compared to the
standard unreachable() with no arguments.
This change improves the chances of building mesa with the C23 standard,
which for instance is the default in recent AOSP versions.
All the instances of the macro, including the definition, were updated
with the following command line:
git grep -l '[^_]unreachable(' -- "src/**" | sort | uniq | \
while read file; \
do \
sed -e 's/\([^_]\)unreachable(/\1UNREACHABLE(/g' -i "$file"; \
done && \
sed -e 's/#undef unreachable/#undef UNREACHABLE/g' -i src/intel/isl/isl_aux_info.c
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36437>
Keep the support in gen_sort_xml.py to allow it still convert
old MRs into the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
And change the gen_sort_xml.py script to default to the new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Change code to temporarily support both the start/end old format and the
dword/bits new format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Add a `--bits-format` argument to normalize the output to either of the
formats described below. For now, defaults to the old format.
The documentation in PRMs and BSpec describe the fields with the dword
and the bit range. Using the same convention makes easier to spot
issues.
Old format:
```
<field name="Disable SLM Read Merge Optimization" start="38" end="38" type="bool" />
<field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
```
New format:
```
<field name="Disable SLM Read Merge Optimization" dword="1" bits="6:6" type="bool" />
<field name="Pixel Async Compute Thread Limit" dword="1" bits="9:7" type="uint" prefix="PACTL">
```
For Groups, we store the dword and if needed a offset_bits, in case
a group starts in a non-aligned position. Size and count for groups are
not changed.
Do this first for gen_sort_tags.py in case is convenient to have for the
stable tree to convert future patches from the new back into the old
format. Later patches will add support to the rest of the code.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
Avoid noise when changing to the new GenXML field format -- which would
try to also sort it. Also add this file to be checked as part of tests.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36138>
So that the body field has the same name in COMPUTE_WALKER &
EXECUTE_INDIRECT_DISPATCH.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36146>
This generator scripts uses the `write` function that, unlike `print`,
doesn't print a trailing newline. So let's add one to the template.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35697>
Load the format enum and then just go through a series of :
if format == R16G16B16A16_UNORM
color = lower_r32g32_uint_tor_r16g16b16a16_unorm(color)
else if format == R16G16B16A16_SNORM
...
For Gfx12.5, there is no in-shader conversion.
For Gfx12/11, the in-shader conversion covers the following formats :
- ISL_FORMAT_R10G10B10A2_UNORM
- ISL_FORMAT_R10G10B10A2_UINT
- ISL_FORMAT_R11G11B10_FLOAT
For Gfx9, the following formats :
- ISL_FORMAT_R16G16B16A16_UNORM
- ISL_FORMAT_R16G16B16A16_SNORM
- ISL_FORMAT_R10G10B10A2_UNORM
- ISL_FORMAT_R10G10B10A2_UINT
- ISL_FORMAT_R8G8B8A8_UNORM
- ISL_FORMAT_R8G8B8A8_SNORM
- ISL_FORMAT_R16G16_UNORM
- ISL_FORMAT_R16G16_SNORM
- ISL_FORMAT_R11G11B10_FLOAT
- ISL_FORMAT_R8G8_UNORM
- ISL_FORMAT_R8G8_SNORM
- ISL_FORMAT_R16_UNORM
- ISL_FORMAT_R16_SNORM
- ISL_FORMAT_R8_UNORM
- ISL_FORMAT_R8_SNORM
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22524>
One more instruction were the MOCS value was splited into two
registes.
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34592>
Xe2 changed the MOCS field in few instructions, those now have a field
for the MOCS index and other the encryption enable bit but ISL returns
the combination of both aka MEMORY_OBJECT_CONTROL_STATE.
To minimize changes I have added 2 macros to extract the values
from the value returned by isl.
From all the instructions changed Mesa only make use of two, so the
other instruction will be handled in the next patch.
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34592>
Copy engine is not used in gfx12 platforms on ANV but that is possible
in Iris.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34560>
Before:
30453 ./build/src/intel/genxml/gen125_pack.h
After:
17026 ./build/src/intel/genxml/gen125_pack.h
21589 ./build/src/intel/genxml/gen125_video_pack.h
The idea is to have fewer line to parse in each genX_*.c file.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
