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intel/genxml: Update CS_CHICKEN1 register field

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36337>
This commit is contained in:
Sagar Ghuge 2025-07-23 13:11:44 -07:00 • committed by Marge Bot
parent 47c9c1869c
commit 9ae09d521c
2 changed files with 12 additions and 0 deletions
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6
src/intel/genxml/gen120.xml
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@ -2253,8 +2253,14 @@
<value name="Mid-cmdbuffer Preemption" value="0" />
<value name="Object Level Preemption" value="1" />
</field>
<field name="Media And GPGPU Pre-emption Control" dword="0" bits="2:1" type="uint">
<value name="Mid-thread Pre-emption" value="0" />
<value name="Thread Group Pre-emption" value="1" />
<value name="Command Level Pre-emption" value="2" />
</field>
<field name="Disable Preemption and High Priority Pausing due to 3DPRIMITIVE Command" dword="0" bits="10:10" type="bool" />
<field name="Replay Mode Mask" dword="0" bits="16:16" type="bool" />
<field name="Media And GPGPU Pre-emption Control Mask" dword="0" bits="18:17" type="uint" />
<field name="Disable Preemption and High Priority Pausing due to 3DPRIMITIVE Command Mask" dword="0" bits="26:26" type="bool" />
</register>
<register name="FF_MODE2" length="1" num="0x6604">

6
src/intel/genxml/gen90.xml
View file

@ -4115,7 +4115,13 @@
<value name="Mid-cmdbuffer Preemption" value="0" />
<value name="Object Level Preemption" value="1" />
</field>
<field name="Media And GPGPU Pre-emption Control" dword="0" bits="2:1" type="uint">
<value name="Mid-thread Pre-emption" value="0" />
<value name="Thread Group Pre-emption" value="1" />
<value name="Command Level Pre-emption" value="2" />
</field>
<field name="Replay Mode Mask" dword="0" bits="16:16" type="bool" />
<field name="Media And GPGPU Pre-emption Control Mask" dword="0" bits="18:17" type="uint" />
</register>
<register name="CS_DEBUG_MODE2" length="1" num="0x20d8">
<field name="3D Rendering Instruction Disable" dword="0" bits="0:0" type="bool" />