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intel/genxml: Disable compute walker mid-thread preemption
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On Xe, we have this bit reversed. It's called Thread preemption Disable.
On Xe2+ (Bspec 56590), it's called Thread preemption with option
enabled/disabled.

AFAIK, we don't support mid-thread preemption. This patch set values
properly according to bspec.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41120>
This commit is contained in:
Sagar Ghuge 2026-04-22 22:16:20 -07:00 • committed by Marge Bot
parent b3fe0cb34e
commit e65e62b17f
2 changed files with 2 additions and 2 deletions
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2
src/intel/genxml/xe2.xml
View file

@ -64,7 +64,7 @@
<value name="Ftz" value="0" />
<value name="SetByKernel" value="1" />
</field>
<field name="Thread Preemption" dword="2" bits="20:20" type="bool" default="1" />
<field name="Thread Preemption" dword="2" bits="20:20" type="bool" />
<field name="Sampler Count" dword="3" bits="4:2" type="uint">
<value name="No samplers used" value="0" />
<value name="Between 1 and 4 samplers used" value="1" />

2
src/intel/genxml/xe3.xml
View file

@ -53,7 +53,7 @@
<value name="Ftz" value="0" />
<value name="SetByKernel" value="1" />
</field>
<field name="Thread Preemption" dword="2" bits="20:20" type="bool" default="1" />
<field name="Thread Preemption" dword="2" bits="20:20" type="bool" />
<field name="Registers Per Thread" dword="2" bits="30:26" type="uint" />
<field name="Sampler Count" dword="3" bits="4:2" type="uint">
<value name="No samplers used" value="0" />