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intel: rename DCFlushEnable to ForceDeviceCoherency

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38707>
This commit is contained in:
Lionel Landwerlin 2024-10-29 15:54:12 +02:00 • committed by Marge Bot
parent e55a7bc83a
commit 682f907228
3 changed files with 18 additions and 1 deletions
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5
src/gallium/drivers/iris/iris_state.c
View file

@ -10421,7 +10421,12 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
#endif
pc.LRIPostSyncOperation = NoLRIOperation;
pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE;
#if GFX_VER >= 20
pc.ForceDeviceCoherency = flags & (PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_DATA_CACHE_FLUSH);
#else
pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH;
#endif
pc.StoreDataIndex = 0;
pc.CommandStreamerStallEnable = flags & PIPE_CONTROL_CS_STALL;
#if GFX_VERx10 < 125

2
src/intel/genxml/gen200.xml
View file

@ -1595,7 +1595,7 @@
<field name="State Cache Invalidation Enable" dword="1" bits="2:2" type="bool" />
<field name="Constant Cache Invalidation Enable" dword="1" bits="3:3" type="bool" />
<field name="VF Cache Invalidation Enable" dword="1" bits="4:4" type="bool" />
<field name="DC Flush Enable" dword="1" bits="5:5" type="bool" />
<field name="Force Device Coherency" dword="1" bits="5:5" type="bool" />
<field name="Pipe Control Flush Enable" dword="1" bits="7:7" type="bool" />
<field name="Notify Enable" dword="1" bits="8:8" type="bool" />
<field name="Indirect State Pointers Disable" dword="1" bits="9:9" type="bool" />

12
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -55,7 +55,12 @@ static enum anv_pipe_bits
convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
enum anv_pipe_bits bits = 0;
bits |= (pc->DepthCacheFlushEnable) ? ANV_PIPE_DEPTH_CACHE_FLUSH_BIT : 0;
#if GFX_VER >= 20
bits |= (pc->ForceDeviceCoherency) ? (ANV_PIPE_DATA_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT) : 0;
#else
bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
#endif
#if GFX_VERx10 >= 125
bits |= (pc->PSSStallSyncEnable) ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0;
#endif
@ -2678,7 +2683,12 @@ emit_pipe_control(struct anv_batch *batch,
pipe.HDCPipelineFlushEnable = bits & ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
#endif
pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
#if GFX_VER >= 20
pipe.ForceDeviceCoherency = bits & (ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT);
#else
pipe.DCFlushEnable = bits & ANV_PIPE_DATA_CACHE_FLUSH_BIT;
#endif
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
@ -3278,7 +3288,9 @@ genX(cmd_buffer_set_protected_memory)(struct anv_cmd_buffer *cmd_buffer,
}
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.PipeControlFlushEnable = true;
#if GFX_VER < 20
pc.DCFlushEnable = true;
#endif
pc.RenderTargetCacheFlushEnable = true;
pc.CommandStreamerStallEnable = true;
if (enabled)