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intel/genxml: Add new State Cache Perf Fix Disabled field

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This patch adds new field to COMMON_SLICE_CHICKEN3 register.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39982>
This commit is contained in:
Sagar Ghuge 2021-01-28 09:33:50 -08:00 • committed by Marge Bot
parent adf18761f8
commit 5391e37b6b
1 changed files with 2 additions and 0 deletions
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src/intel/genxml/gen110.xml
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@ -3207,7 +3207,9 @@
</register>
<register name="COMMON_SLICE_CHICKEN3" length="1" num="0x7304">
<field name="PS Thread Panic Dispatch" dword="0" bits="7:6" type="uint" />
<field name="State Cache Perf Fix Disabled" dword="0" bits="13:13" type="bool"/>
<field name="PS Thread Panic Dispatch Mask" dword="0" bits="23:22" type="uint" />
<field name="State Cache Perf Fix Disabled Mask" dword="0" bits="29:29" type="bool"/>
</register>
<register name="COMMON_SLICE_CHICKEN4" length="1" num="0x7300">
<field name="Enable Hardware Filtering in WM" dword="0" bits="5:5" type="bool" />