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Author SHA1 Message Date
Alyssa Rosenzweig
b8bd356dff panfrost: Allow tiling on RECT textures 
Except for the norm coords bit, they're identical to 2D.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
c41cf03589 panfrost: Allow bpp24 tiling 
It's dumb that we have to but it does help RGB8 nontrivially. Alas.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
48cc608859 panfrost: Don't zero staging buffer for tiling 
It's a little less safe but the memset does take time during
initialization. v3d doesn't either, so I think  it's ok.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
9f2997dad0 panfrost: Don't set PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY 
I'm not aware of any reason this might be necessary, let's avoid the
translate.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
5a4eeb21bf panfrost: Fill in SCALED formats to format table 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
98fc955c6e panfrost: Remove deadcode 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:32 -04:00
Alyssa Rosenzweig
794c239a99 panfrost: Keep cached BOs mmap'd 
It doesn't make sense to munmap/mmap repeatedly; they're mapped GPU-side
anyway. So just munmap on free, which will happen in low-mem regardless.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>
 2020-05-21 14:43:31 -04:00
Alyssa Rosenzweig
485ec76108 panfrost: Guard experimental fp16 behind debug flag 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
e6293425bf pan/mdg: Pack 8-bit swizzles in 16-bit ops 
Let's inch closer to 8-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
ca48143ec4 pan/mdg: Implement condense_writemask for 8-bit 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
f768cb04ed pan/mdg: Implement vector constant printing for 8-bit 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
28201af080 pan/mdg: Use shifts instead of division for RA sizes 
We're only dealing with powers-of-two, so this eliminates potential
issues with divisions-by-zero that are otherwise hacked around. Probably
faster too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
3d435b334b pan/mdg: Pack barriers correctly 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
fde1f2b7cb pan/mdg: Fix type checking issues with compute 
SSBO and barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
4e4c9f5f5a pan/mdg: Separately pack constants to the upper half 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
d475d19f09 pan/mdg: Only combine 16-bit constants to lower half 
We can't swizzle both halves simultaneously.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
8b4e278628 pan/mdg: Factor out mir_adjust_constant 
Each source is semi-independent, we don't need the extra indentation
when the logic is already so complex.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
b833702cc1 pan/mdg: Print constant vectors less wrong 
For !32-bit types, we need to pay attention to rep_low/high/half to
determine the effective swizzle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
cd26bd9425 pan/mdg: Round up bytemasks when spilling 
So we can pack the spills for <32-bit types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
68d2a889b7 pan/mdg: Print mask when dest=0 
Forgot this convention differs from Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
553c2cf16b pan/mdg: Set RA bounds for fp16 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
b91d71597e pan/mdg: Eliminate load_64 
It can always be inferred from the types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
1ff2cabe87 pan/mdg: Use type size to determine alignment 
Generally, f16 needs to be aligned to 16-bit, f32 to 32-bit, ...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
51582e5454 pan/lcra: Allow per-variable bounds to be set 
Different variables need to respect different bounds. In general,
16-bytes is okay, but for 4-channel 16-bit vectors, we can't cross 8
byte boundaries (else the swizzles will not be packable after), so we
update LCRA to allow this more general form.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
0737080ba6 pan/lcra: Remove unused alignment parameters 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
21405f6fcf pan/mdg: Ignore dest.type when offseting load swizzle 
It's always as-if 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
4f5bad649b pan/mdg: Don't generate conversions for fp16 LUTs 
We can just set the register mode appropriately and then we don't have
to care anywhere else, and there's no extra NIR to chew through. Make
sure we include sqrt too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
6b023b3545 pan/mdg: Implement b2f16 
...as iand

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
1108eaa90d pan/mdg: Streamline dest_override handling 
We can pass it all off to emit time, and let the types in the IR do the
heavylifting in the meantime, which is a lot easier to get right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
1e4793a95c pan/mdg: Remove redundant redundancy 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
1cd65353c9 pan/mdg: Defer modifier packing until emit time 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
edf1479bea pan/mdg: Remove promote_float pass 
Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
72c1e3a66a pan/mdg: Promote imov to fmov on a NIR level 
Avoids dedicated MIR promote_fmov pass which is unnecessary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
3cfe2fc1b1 pan/mdg: Identify scalar integer mods 
Symmetric with vector mods, except for normal which is packed as
sign-extend. (flag 2 never seen in the wild)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
d4a42a78d8 pan/mdg: Use type to determine triviality of a move 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
df3d932bb4 pan/mdg: Use src_types to determine size in scheduling 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
95dd478ed3 pan/mdg: Add abs/neg/shift modifiers to IR 
Rather than twiddling them into the ALU packed field.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
31e13956e1 pan/mdg: Explain ld/st sign/zero extension 
Now we know why there are duplicates :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
dbcae7c667 pan/mdg: Respect !32-bit sizes in RA 
So we can take advantage of mediump.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
8c012c8f8b pan/mdg: Handle dest up/lower correctly with swizzles 
During emit time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
8084fc3b66 pan/mdg: Include more types 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
e9a4bd90a8 pan/mdg: Remove mir_get_alu_src 
Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:14 +00:00
Alyssa Rosenzweig
9915bb2c40 pan/mdg: Remove mir_*size routines 
We'd rather use the actual type information than inferring modes all
over the place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Alyssa Rosenzweig
40e9bee714 pan/mdg: Fix constant combining crash 
We need to round up.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Alyssa Rosenzweig
eb28a3669b pan/mdg: Handle comparisons in fp16 path 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
 2020-05-21 17:49:13 +00:00
Samuel Pitoiset
2d4493ee11 aco: sign-extend the input and identity for 8-bit subgroup operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset
c76595aec2 aco: use a temporary SGPR for 8-bit/16-bit literal reduction identities 
Otherwise, the compiler overwrites s0 which contains the exec mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset
b3c87c52ea aco: implement 8-bit/16-bit nir_intrinsic_quad_* 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset
dfa62d97a0 aco: implement 8-bit/16-bit nir_intrinsic_{shuffle,_read_invocation} 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00
Samuel Pitoiset
f03e56eaf0 aco: implement 8-bit/16-bit nir_intrinsic_read_first_invocation 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>
 2020-05-21 15:06:48 +00:00