The option's description is:
> Whether to use LLVM for the Gallium draw module, if LLVM is included.
Let's disable it right away if LLVM is disabled, to avoid some
configurations from failing.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38558>
Prior to commit b8b38d38b1 ("meson: reinstate LLVM requirement for r300
and enforce it for i915 too") it was possible to build and use r300 for
architectures that do not have LLVM (e.g., alpha).
The only SWTCL chips are integrated graphics in x86 systems, and are not
available in discrete cards.
Fixes: b8b38d38b1 ("meson: reinstate LLVM requirement for r300 and enforce it for i915 too")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38580>
Swizzle can include PIPE_SWIZZLE_0/_1 (4 and 5) which result in indexing
beyond the channel array.
Reported-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Fixes: 76e350671f ("freedreno/a6xx: Sysmem clear fixes")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38593>
This allows us to fully define crashdec in all situations, even when
its essential dependencies are not found. The result is that if
libarchive or lua is not found, the tests become disabled automatically.
This avoids the situation where `-Dbuild-tests=true`, but at least one
of libarchive and lua are missing, in which `crashdec` is used
undefined.
Acked-by: Rob Clark <rob.clark@oss.qualcomm.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38579>
There are cases where the freedreno `crashdec` program will not be
built, but will still be used. By making dep_lua a disabler, we move
closer to being able to have those tests automatically disabled when
crashdec isn't built.
Acked-by: Rob Clark <rob.clark@oss.qualcomm.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38579>
This is the last level layer of emission, we want the tracking to be
added above that, so that when flushing of previously accumulated
reasons happens, another pointless reason isn't added.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38542>
Removes encoder's use resource utilities. All memory allocations
are now tracked in the VkDevice level residency set. This is
accomplished by tracking buffer objects at create/destroy.
Also removes all descriptor set residency tracking since it is
no longer needed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38505>
Mesa builds using -Dperfetto=true generate a pps-producer binary.
Include it in the artifacts for use in runtime performance tracing
tests.
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
Enable Perfetto tracing support in Mesa's x86_64/arm64 builds for Linux
and Android. This enables GPU performance counter collection via pps and
sets up the environment for runtime GL tests with support for CPU, GPU
and system-wide tracing. Information captured by Perfetto will provide
driver developers insight into the test environment and help identify
factors affecting performance.
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38517>
This should be ignored on non-compute stages but AGX changes 3D shaders
to compute without setting the workgroup size and blows up if it claims
variable workgroups. The safest thing is to only set it from
spirv_to_nir for stages that actually have workgroups.
Fixes: 6d9f563960 ("spirv: Assume variable workgroup size unless it's set")
LoLed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38555>
This is strictly a GL thing. iris can manage it in its own program keys
without polluting the compiler with stuff nobody else cares about.
We can also drop a lot of padding that was introduced in commit
a18835a9ca which doesn't appear to be
necessary.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
We're storing iris keys here, not brw keys. This worked because brw
keys are larger so you could fit any iris key in the memory.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38556>
The versioning scheme changed in v45.0 (the previous version was
3.48.0). As such, this version check would wrongly accept e.g. 48.0.
Fixes: e9341568fa ("meson: require sysprof-capture-4 >= 4.49.0")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38557>
We don't have to enter the lower-IO-to-temps block for TCS at all.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38470>
Previously legacy_gs_info calculated based on
gs_info->legacy_gs_info.esgs_itemsize which is calculated based on gs
input varyings.
However, when using ESO vs/tes can have outputs not read by gs, which
leads to underestimating LDS usage.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38514>
One might think that the `64B` bit might be affecting just the
memory size, but that's not the case as it affects the register
count too. Setting `64B` with `CNT` of `1` actually copies 2
registers, and not 1.
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38535>
This makes it possible for these to be used in static_asserts or if
we want to get a register offset (gen agnostic) and have it be
marked as constexpr. E.g.
```
constexpr uint32_t src_reg = __TPL1_A2D_SRC_TEXTURE_BASE<CHIP>({}).reg;
```
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38549>
Attempting to separate things out by gen is a bit arbitrary. And gets
increasingly awkward as we introduce gen8 support, which builds on gen7
but changes some a6xx values.
Just move it all into a single 'props' struct.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
