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anv: put more readable PIPE_CONTROL reasons
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38542>
This commit is contained in:
Lionel Landwerlin
parent
6d98fdb3ec
commit
7c193ffef1
1 changed files with 58 additions and 46 deletions
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@ -287,15 +287,16 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
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*
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* Render target cache flush before SBA is required by Wa_18039438632.
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*/
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genx_batch_emit_pipe_control(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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genX(batch_emit_pipe_control)(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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#if GFX_VER >= 12
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ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
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ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
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#else
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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#endif
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT);
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT,
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"pre STATE_BASE_ADDRESS flush");
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#if INTEL_NEEDS_WA_1607854226
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/* Wa_1607854226:
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@ -373,9 +374,10 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer)
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(intel_needs_workaround(device->info, 16013000631) ?
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ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT : 0);
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genx_batch_emit_pipe_control(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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bits);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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bits,
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"Post STATE_BASE_ADDRESS invalidate");
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assert(cmd_buffer->state.current_db_mode !=
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ANV_CMD_DESCRIPTOR_BUFFER_MODE_UNKNOWN);
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@ -429,10 +431,11 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer)
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* Prior to do the invalidation, we need a CS_STALL to ensure that all work
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* using surface states has completed.
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*/
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genx_batch_emit_pipe_control(&cmd_buffer->batch,
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cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_CS_STALL_BIT);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_CS_STALL_BIT,
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"pre BINDING_TABLE_POOL_ALLOC stall");
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anv_batch_emit(
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&cmd_buffer->batch, GENX(3DSTATE_BINDING_TABLE_POOL_ALLOC), btpa) {
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btpa.BindingTablePoolBaseAddress =
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@ -440,11 +443,12 @@ genX(cmd_buffer_emit_bt_pool_base_address)(struct anv_cmd_buffer *cmd_buffer)
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btpa.BindingTablePoolBufferSize = device->physical->va.binding_table_pool.size / 4096;
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btpa.MOCS = mocs;
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}
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genx_batch_emit_pipe_control(&cmd_buffer->batch,
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cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_STATE_CACHE_INVALIDATE_BIT);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch,
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cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_STATE_CACHE_INVALIDATE_BIT,
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"post BINDING_TABLE_POOL_ALLOC invalidate");
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#else /* GFX_VERx10 < 125 */
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genX(cmd_buffer_emit_state_base_address)(cmd_buffer);
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@ -1527,10 +1531,11 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
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* while the pipeline is completely drained and the caches are flushed,
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* which involves a first PIPE_CONTROL flush which stalls the pipeline...
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*/
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genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT,
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"L3 config pc0");
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/* ...followed by a second pipelined PIPE_CONTROL that initiates
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* invalidation of the relevant caches. Note that because RO invalidation
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@ -1546,20 +1551,22 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
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* already guarantee that there is no concurrent GPGPU kernel execution
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* (see SKL HSD 2132585).
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*/
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genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
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ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
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ANV_PIPE_STATE_CACHE_INVALIDATE_BIT);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
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ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
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ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
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ANV_PIPE_STATE_CACHE_INVALIDATE_BIT,
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"L3 config pc1");
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/* Now send a third stalling flush to make sure that invalidation is
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* complete when the L3 configuration registers are modified.
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*/
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genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT);
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genX(batch_emit_pipe_control)(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline,
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ANV_PIPE_DATA_CACHE_FLUSH_BIT |
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ANV_PIPE_CS_STALL_BIT,
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"L3 config pc2");
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genX(emit_l3_config)(&cmd_buffer->batch, cmd_buffer->device, cfg);
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#endif /* GFX_VER >= 11 */
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@ -2677,8 +2684,9 @@ genX(batch_set_preemption)(struct anv_batch *batch,
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}
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/* Wa_16013994831 - we need to insert CS_STALL and 250 noops. */
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genx_batch_emit_pipe_control(batch, device->info, current_pipeline,
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ANV_PIPE_CS_STALL_BIT);
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genX(batch_emit_pipe_control)(batch, device->info, current_pipeline,
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ANV_PIPE_CS_STALL_BIT,
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"Wa_16013994831");
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for (unsigned i = 0; i < 250; i++)
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anv_batch_emit(batch, GENX(MI_NOOP), noop);
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@ -5343,10 +5351,11 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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* This also seems sufficient to handle Wa_14014097488 and
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* Wa_14016712196.
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*/
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genx_batch_emit_pipe_control_write(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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WriteImmediateData,
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device->workaround_address, 0, 0);
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genX(batch_emit_pipe_control_write)(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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WriteImmediateData,
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device->workaround_address, 0, 0,
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"Wa_1408224581/14014097488/14016712196");
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}
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if (info.depth_surf)
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@ -5395,10 +5404,11 @@ cmd_buffer_emit_cps_control_buffer(struct anv_cmd_buffer *cmd_buffer,
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* Emit dummy pipe control after state that sends implicit depth flush.
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*/
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if (intel_needs_workaround(device->info, 14016712196)) {
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genx_batch_emit_pipe_control_write(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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WriteImmediateData,
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device->workaround_address, 0, 0);
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genX(batch_emit_pipe_control_write)(&cmd_buffer->batch, device->info,
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cmd_buffer->state.current_pipeline,
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WriteImmediateData,
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device->workaround_address, 0, 0,
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"Wa_14016712196");
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}
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#endif /* GFX_VERx10 >= 125 */
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@ -6240,12 +6250,13 @@ void genX(CmdSetEvent2)(
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pc_bits |= ANV_PIPE_CS_STALL_BIT;
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}
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genx_batch_emit_pipe_control_write
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genX(batch_emit_pipe_control_write)
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(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline, WriteImmediateData,
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anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
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event->state),
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VK_EVENT_SET, pc_bits);
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VK_EVENT_SET, pc_bits,
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"vkCmdSetEvent2");
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break;
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}
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@ -6285,13 +6296,14 @@ void genX(CmdResetEvent2)(
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pc_bits |= ANV_PIPE_CS_STALL_BIT;
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}
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genx_batch_emit_pipe_control_write
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genX(batch_emit_pipe_control_write)
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(&cmd_buffer->batch, cmd_buffer->device->info,
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cmd_buffer->state.current_pipeline, WriteImmediateData,
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anv_state_pool_state_address(&cmd_buffer->device->dynamic_state_pool,
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event->state),
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VK_EVENT_RESET,
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pc_bits);
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pc_bits,
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"vkCmdResetEvent2");
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break;
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}
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