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Author SHA1 Message Date
Caio Oliveira
0c03018abf intel/compiler/xe2: URB fence uses LSC now 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
623465e26d intel/compiler/xe2: Update fs_visitor::emit_urb_writes to not assume SIMD8 
v2: Account for 512b physical registers which causes the URB handle to be in FIXED_GFR 2 instead of 1.

XXX - Use fs_builder::vgrf() instead of open-coded dispatch_width calculations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Kenneth Graunke
4fffdbbfa2 intel/fs: Fix Xe2 URB read/lowering with per-slot offsets 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
c28539a2fe intel/compiler: Use enum xe2_lsc_cache_load on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
8d27b327f2 intel/compiler: Add enum xe2_lsc_cache_load 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
09fc9ff114 intel/compiler: Use enum xe2_lsc_cache_store on xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Jordan Justen
c54eff2e03 intel/compiler: Add enum xe2_lsc_cache_store 
Rework:
 * Rohan: Fix enum value for L1WB_L3WB
 * Fix write-through comments (Ken)

Ref: bspec 71167
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
1245020282 intel/compiler: add initial support for URB_LOGICAL_SRC_CHANNEL_MASK to lower_urb_write_logical_send_xe2 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Marcin Ślusarz
9c90377962 intel/compiler: add lsc_msg_desc_wcmask 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
feec9166cd intel/compiler/xe2: Handle new URB write messages 
Rework:
 * idr v1: Fix compilation error.
 * idr v2: Add support for per-channel offsets.
 * idr v3: get_lowered_simd_width is 16 on Xe2+.
 * idr v4: Add disassembly support.  Add validation support.
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Ian Romanick
fa53a7d241 intel/compiler/xe2: Handle new URB read messages 
Rework:
 * Sqaushed in changes Marcin Ślusarz's patches:
   * "intel/compiler: skip adding 0 to payload address"
   * "intel/compiler/xe2: drop masking off top 8 bits of URB handle"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25195>
 2023-09-27 23:57:25 +00:00
Caio Oliveira
c487ba26ca intel/compiler: Don't store stage name and abbrev 
Those are used in the failure paths and are easily retriavable from the
stage itself, so no need to store them.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25367>
 2023-09-26 18:12:53 -07:00
Caio Oliveira
1cdc4be14b intel/compiler: Don't allocate memory for SIMD select error handling 
The position in the error array already indicate the SIMD in question,
so take off all the formatted printing from the errors -- which in some
cases were just not needed.  We lose a little bit of extra context but
it is all easily derivable from the message and the SIMD.

This also will remove the overhead when SIMD selection is being used to
just to find the selected dispatch width -- at a point where the shaders
were already compiled -- and the errors are not used at all.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9849
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25336>
 2023-09-22 16:23:02 +00:00
Jordan Justen
f1b9b7f955 intel/fs: Update SSBO & shared uniform block loads for Xe2 
Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.

Ref: a358b97c58 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9fb2b12c99 intel/compiler: Update RT stack_id access for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
d371565d34 intel/compiler: Update ray-tracing intrinsic lowering for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
3d744a6890 intel/compiler: Update lower_trace_ray_logical_send() for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9e43fa09a6 intel/compiler: Update emit_rt_lsc_fence() for Xe2 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:16 -07:00
Jordan Justen
9846dd798b intel/compiler: Update opt_split_sends() for Xe2 reg size 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 23:06:04 -07:00
Jordan Justen
727ab2c11d intel/compiler/fs: Support Xe2 reg size in assign_curb_setup 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
cef4d53daf intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg(). 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
fe3d90aedf intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
791d040104 intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
ac4f598577 intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
37e280f28a intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
dd632bf527 intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
8944ac7d6c intel/fs/xe2+: Update BS payload setup for Xe2 reg size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
14e1b9ee69 intel/fs/xe2+: Update TES payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
4b3243104c intel/fs/xe2+: Update TCS payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
6195eac210 intel/fs/xe2+: Update GS payload setup for Xe2 reg size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
28744c8954 intel/compiler/xe2: Account for reg_unit() in TES intrinsics 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Caio Oliveira
9859f5b4d2 intel/compiler/xe2: Account for reg_unit() in TCS intrinsics 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
610daa3166 intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
c9f2857546 intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
ef817650c9 intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Ian Romanick
0b23df3951 intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size 
[ Francisco Jerez: Simplify. ]

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
42b90f05f6 intel/compiler: Adjust barrier emission for Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
8b1dc77521 intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
4de065f6a2 intel/compiler: Adjust fence message lengths for new register width on Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Rohan Garg
e1289d6135 intel/compiler: Adjust CS payload registers for new register width on Xe2+ 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
150b3e87c8 intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
24dcc3269b intel/fs/xe2+: Update encoding of FB write message payload. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
a573531785 intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
17ef5e7ead intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
6423cb9bfa intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
00b614a5a7 intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
421d43fe62 intel/fs/xe2+: Fixes for increased accumulator register width. 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
80e9031b44 intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
571ddf8516 intel/fs/xe2+: Fix payload node live range calculations for change in register size. 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00
Francisco Jerez
2b7419d090 intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges(). 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
 2023-09-20 17:19:36 -07:00