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intel/compiler: Adjust fence message lengths for new register width on Xe2+

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
This commit is contained in:
Rohan Garg 2022-07-22 13:33:17 +02:00 • committed by Jordan Justen
parent e1289d6135
commit 4de065f6a2
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_eu_emit.c
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@ -3274,9 +3274,9 @@ gfx12_set_memory_fence_message(struct brw_codegen *p,
enum brw_message_target sfid,
uint32_t desc)
{
const unsigned mlen = 1; /* g0 header */
const unsigned mlen = 1 * reg_unit(p->devinfo); /* g0 header */
/* Completion signaled by write to register. No data returned. */
const unsigned rlen = 1;
const unsigned rlen = 1 * reg_unit(p->devinfo);
brw_inst_set_sfid(p->devinfo, insn, sfid);