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Author SHA1 Message Date
Mike Blumenkrantz
a4c0f5ba6f svga: simplify some surface management 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40462>
 2026-03-23 16:58:13 +00:00
Mike Blumenkrantz
17d9f1dc64 llvmpipe: delete pipe_context surface hooks 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40462>
 2026-03-23 16:58:12 +00:00
Mike Blumenkrantz
fa350781ed svga: delete pipe_context surface hooks 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40462>
 2026-03-23 16:58:12 +00:00
Mike Blumenkrantz
5e2ecd64b0 softpipe: delete pipe_context::create_surface 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40462>
 2026-03-23 16:58:11 +00:00
Pierre-Eric Pelloux-Prayer
98cdcf9467 radeonsi/test: update failures 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40372>
 2026-03-23 14:53:01 +00:00
Pierre-Eric Pelloux-Prayer
88986dcc9c radeonsi: account for outputs_written when updating spi_shader_col_format 
Variants can modify which outputs get written so we must update
these fields otherwise spi_shader_col_format will be incorrect.

This can happen for instance with uniforms inlining:

   uniform bool depth_only;
   void main() {
      if (depth_only) return;
      ...
   }

When depth_only is true, this shader becomes empty after uniforms
inlining but spi_shader_col_format wasn't updated properly,
causing a hang.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14737
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40372>
 2026-03-23 14:53:01 +00:00
Pierre-Eric Pelloux-Prayer
da7c515783 radeonsi: move spi_shader_*_format to si_shader_variant_info 
Variants can affect theses value so it's best to store them
in this struct.

No functional changes.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40372>
 2026-03-23 14:53:01 +00:00
Tomeu Vizoso
db5a1ed2fa rocket: Skip all synthetic tests as we now have several real models 
And sync the baseline with the new models that were recently added.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40166>
 2026-03-23 12:57:09 +00:00
Tomeu Vizoso
15f0c245c8 ethosu: Set test baseline for the Corstone 1000 (U85)
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:59 +00:00
Tomeu Vizoso
ac0d6e7b7c ethosu: Properly emit IFM_BROADCAST and IFM2_BROADCAST on U85 
On U85, both NPU_SET_IFM_BROADCAST and NPU_SET_IFM2_BROADCAST must be
emitted for elementwise operations, matching Vela's GenerateInputBroadcast.

Add calc_broadcast_mode() matching Vela's CalculateBroadcast(): broadcasts
a dimension of shape1 when it is 1 and shape2 is larger, producing a
broadcast_mode bitmask (H=1, W=2, C=4, SCALAR=8).

Split emit_ifm2_broadcast into U65 (legacy bitfields) and U85 paths.
The U85 path emits both IFM_BROADCAST and IFM2_BROADCAST using
calc_broadcast_mode in each direction.

Also fix emit_eltwise to call emit_ifm2_precision instead of
emit_ifm_broadcast for U85, which was emitting 0 instead of the
required IFM2_PRECISION register.

Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:59 +00:00
Tomeu Vizoso
2a6d181bc6 ethosu: Fix scalar ADD on U85 
They added new registers tot he command stream, with a new bitfield
layout.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:59 +00:00
Tomeu Vizoso
818e1835d7 ethosu: map BOs at creation time and unmap at destruction 
Map DRM buffer objects once at resource_create and unmap at
resource_destroy, instead of mapping them in buffer_map where they
were never unmapped. This fixes a virtual memory leak that caused
SIGBUS under heavy workloads by exhausting CMA.

Also remove unused phys_addr and obj_addr fields from ethosu_resource,
and add asserts on pipe_buffer_create return values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:58 +00:00
Tomeu Vizoso
f9cd399eb0 ethosu: Fix ublock selection for 8-bit depthwise/pooling on U85-256 
For U85-256 with 8-bit IFM, Vela's _uBlockToOpTable restricts which
microblocks are valid per operation type:

  {2,2,8}  and {4,1,8}:  conv, matmul, vectorprod, reducesum, eltwise, resize
  {2,1,16}:              depthwise, pool, eltwise, reduceminmax, argmax, resize

Mesa's find_ublock() was not enforcing these constraints, allowing
{4,1,8} or {2,2,8} to be selected for depthwise/pooling based on
minimum waste. For depthwise ops with OFM shapes that aligned better
to {4,1,8}, the wrong ublock was chosen, causing incorrect weight
encoding and NPU hangs.

Fix by skipping {4,1,8} and {2,2,8} for depthwise/pooling operations,
matching Vela's operation-validity table.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:58 +00:00
Tomeu Vizoso
dc36a32214 ethosu: Implement simplified scaling for U85 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:58 +00:00
Tomeu Vizoso
dbfbc6eff4 ethosu: Emission changes for U85 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:58 +00:00
Tomeu Vizoso
42082266f0 ethosu: Refactor ethosu_allocate_feature_map to return the new offset 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:58 +00:00
Tomeu Vizoso
fc70406bdd ethosu: Expand pooling to U85 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:57 +00:00
Tomeu Vizoso
a735fe040b ethosu: Improve parallelism by detecting overlaps for BLOCKDEP 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:57 +00:00
Tomeu Vizoso
2cf3d0b273 ethosu: Add a separate scheduler for the U85 
As the performance details have changed quite a bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:57 +00:00
Tomeu Vizoso
82d4f21106 ethosu: Don't emit redundant state changes 
Keep track of the state and only emit meaningful changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:56 +00:00
Tomeu Vizoso
8872f5eea4 ethosu: Add debug option for forcing U85 generation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:56 +00:00
Tomeu Vizoso
45fb8b99df ethosu: Invert lowering order of concatenation suboperations 
Just so we match the order in which Vela assigns offsets to the FMs so
it's easier to diff cmdstream dumps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:56 +00:00
Tomeu Vizoso
d66d2c05d3 ethosu: Switch to the weight encoder from Regor 
We vendor the encoder used in the Regor compiler in Vela, and replace
the previous one that was used by the Python compiler and doesn't
support U85.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:55 +00:00
Tomeu Vizoso
410d74e078 ethosu: Compute is_partkernel during scheduling 
As we need it for encoding the weights.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:55 +00:00
Tomeu Vizoso
3ade0a4dd6 ethosu: Make the UBlock sizes arch-specific 
As U85 has a different configuration.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:55 +00:00
Tomeu Vizoso
91137a9327 ethosu: Let maxblockdeps be arch-specific 
As U85 can have up to 7.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:54 +00:00
Tomeu Vizoso
0af37552a7 ethosu: Add U85 fields, these are compatible with the U65 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:54 +00:00
Tomeu Vizoso
4388f602ed teflon: Fix leak of tensor structs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:53 +00:00
Tomeu Vizoso
47aa30276e ethosu: Update test expectations 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
 2026-03-23 07:45:53 +00:00
Marek Olšák
fa5175023b Final rename of sha1 names to blake3 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
ae9ea27e0d Rename *_sha1 names to *_blake3 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
353fe94c0e Rename SHA1 words to BLAKE3 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
102d41799b Rename more sha and sha1 names to blake3 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
282bd2e6db Rename sha words to blake3 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
d4831aaf5f Rename sha1_* and sha_* names to blake3_* 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:28 +00:00
Marek Olšák
c0ac992a2a Remove mesa-sha1.h 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
53c64973e8 Inline _mesa_sha1_compute/format, remove the other unused ones 
_mesa_sha1_format has a few remaining uses, so it's moved to build_id.c,
which is its last user.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
699f9d7066 Inline _mesa_sha1_init/update/final functions 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
3ae8f910ad Inline SHA1* functions, remove sha1.h 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
a965ada6ee Inline mesa_sha1, SHA1_CTX 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
0da88d237a Inline SHA1_DIGEST_STRING_LENGTH 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
110632f702 Inline SHA1_DIGEST_LENGTH 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
 2026-03-23 07:03:27 +00:00
Marek Olšák
2283244975 nir: change export_amd intrinsics to use target instead of base 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40415>
 2026-03-23 06:10:49 +00:00
Rob Herring (Arm)
6b26cc2df3 ethosu: Fix buffer overrun in stridedslice
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
The slice.begin array length matches the tensor depth which may be less
than 4.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
5e93ab5477 ethosu: Support ReLU activation for ADD ops 
ReLU activations require the minimum to be set to the zero point.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
69d1da3518 teflon: Support ReLU activation for ADD ops 
ADD operations can have fused ReLU activations. Add the setting to the
operation state.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
3780fb8494 ethosu: Handle IFM2 H/W/D broadcast 
If the IFM and IFM2 dimensions are not the same, then the H/W/D broadcast
needs to be enabled.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
1cb46e9304 ethosu: Handle reversing IFM and IFM2 operands 
IFM2 must be scalar or smaller than IFM. If not, then the operands need
to be swapped.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
d962160e95 ethosu: Add scalar ADD support 
An input tensor can contain a single scalar value to add to the IFM.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
5606fd1ea6 ethosu: Add support for 16-bit tensors 
Ethos-U can support 16-bit tensors. So far the driver just assumed 8-bit
tensors.

There's a few cases where 32-bit tensors are supported, but exactly what
those are hasn't been determined, so just reject them for now.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
 2026-03-21 08:32:19 +00:00