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Rename *_sha1 names to *_blake3

Browse source 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
This commit is contained in:
Marek Olšák 2026-03-12 22:44:51 -04:00 • committed by Marge Bot
parent 353fe94c0e
commit ae9ea27e0d
58 changed files with 201 additions and 201 deletions
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8
src/amd/vulkan/radv_pipeline.c
View file

@ -218,7 +218,7 @@ radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPipeline
radv_shader_layout_init(pipeline_layout, out_stage->stage, &out_stage->layout);
vk_pipeline_hash_shader_stage(pipeline_flags, sinfo, NULL, out_stage->shader_sha1);
vk_pipeline_hash_shader_stage(pipeline_flags, sinfo, NULL, out_stage->shader_blake3);
}
void
@ -1148,11 +1148,11 @@ void
radv_pipeline_hash_shader_stage(VkPipelineCreateFlags2 pipeline_flags, const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_shader_stage_key *stage_key, blake3_hasher *ctx)
{
unsigned char shader_sha1[BLAKE3_KEY_LEN];
unsigned char shader_blake3[BLAKE3_KEY_LEN];
vk_pipeline_hash_shader_stage(pipeline_flags, sinfo, NULL, shader_sha1);
vk_pipeline_hash_shader_stage(pipeline_flags, sinfo, NULL, shader_blake3);
_mesa_blake3_update(ctx, shader_sha1, sizeof(shader_sha1));
_mesa_blake3_update(ctx, shader_blake3, sizeof(shader_blake3));
_mesa_blake3_update(ctx, stage_key, sizeof(*stage_key));
}

6
src/amd/vulkan/radv_pipeline_binary.c
View file

@ -190,7 +190,7 @@ radv_create_pipeline_binary_from_shader(struct radv_device *device, const VkAllo
VkResult
radv_create_pipeline_binary_from_rt_shader(struct radv_device *device, const VkAllocationCallbacks *pAllocator,
struct radv_shader *shader, bool is_traversal_shader,
const uint8_t stage_sha1[BLAKE3_KEY_LEN],
const uint8_t stage_blake3[BLAKE3_KEY_LEN],
const struct radv_ray_tracing_stage_info *rt_stage_info, uint32_t stack_size,
struct vk_pipeline_cache_object *nir,
struct util_dynarray *pipeline_binaries, uint32_t *num_binaries)
@ -209,7 +209,7 @@ radv_create_pipeline_binary_from_rt_shader(struct radv_device *device, const VkA
}
_mesa_blake3_init(&ctx);
_mesa_blake3_update(&ctx, stage_sha1, sizeof(*stage_sha1));
_mesa_blake3_update(&ctx, stage_blake3, sizeof(*stage_blake3));
_mesa_blake3_final(&ctx, key);
struct radv_ray_tracing_binary_header header = {
@ -219,7 +219,7 @@ radv_create_pipeline_binary_from_rt_shader(struct radv_device *device, const VkA
.stack_size = stack_size,
};
memcpy(header.stage_sha1, stage_sha1, sizeof(header.stage_sha1));
memcpy(header.stage_blake3, stage_blake3, sizeof(header.stage_blake3));
if (rt_stage_info)
memcpy(&header.stage_info, rt_stage_info, sizeof(header.stage_info));

2
src/amd/vulkan/radv_pipeline_binary.h
View file

@ -34,7 +34,7 @@ VkResult radv_create_pipeline_binary_from_shader(struct radv_device *device, con
VkResult radv_create_pipeline_binary_from_rt_shader(struct radv_device *device, const VkAllocationCallbacks *pAllocator,
struct radv_shader *shader, bool is_traversal_shader,
const uint8_t stage_sha1[BLAKE3_KEY_LEN],
const uint8_t stage_blake3[BLAKE3_KEY_LEN],
const struct radv_ray_tracing_stage_info *rt_stage_info,
uint32_t stack_size, struct vk_pipeline_cache_object *nir,
struct util_dynarray *pipeline_binaries, uint32_t *num_binaries);

2
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -34,7 +34,7 @@ radv_hash_graphics_spirv_to_nir(blake3_hash hash, const struct radv_shader_stage
_mesa_blake3_init(&ctx);
_mesa_blake3_update(&ctx, &stage->key, sizeof(stage->key));
_mesa_blake3_update(&ctx, options, sizeof(*options));
_mesa_blake3_update(&ctx, stage->shader_sha1, sizeof(stage->shader_sha1));
_mesa_blake3_update(&ctx, stage->shader_blake3, sizeof(stage->shader_blake3));
_mesa_blake3_final(&ctx, hash);
}

8
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2376,7 +2376,7 @@ radv_create_gs_copy_shader(struct radv_device *device, struct vk_pipeline_cache
struct radv_shader_stage gs_copy_stage = {
.stage = MESA_SHADER_VERTEX,
.shader_sha1 = {0},
.shader_blake3 = {0},
.key =
{
.optimisations_disabled = gs_stage->key.optimisations_disabled,
@ -2539,7 +2539,7 @@ radv_pipeline_retain_shaders(struct radv_retained_shaders *retained_shaders, str
blob_finish_get_buffer(&blob, &retained_shaders->stages[s].serialized_nir,
&retained_shaders->stages[s].serialized_nir_size);
memcpy(retained_shaders->stages[s].shader_sha1, stages[s].shader_sha1, sizeof(stages[s].shader_sha1));
memcpy(retained_shaders->stages[s].shader_blake3, stages[s].shader_blake3, sizeof(stages[s].shader_blake3));
memcpy(&retained_shaders->stages[s].key, &stages[s].key, sizeof(stages[s].key));
stages[s].feedback.duration += os_time_get_nano() - stage_start;
@ -2577,7 +2577,7 @@ radv_pipeline_import_retained_shaders(const struct radv_device *device, struct r
stages[s].stage = s;
stages[s].nir = nir_deserialize(NULL, options, &blob_reader);
stages[s].entrypoint = nir_shader_get_entrypoint(stages[s].nir)->function->name;
memcpy(stages[s].shader_sha1, retained_shaders->stages[s].shader_sha1, sizeof(stages[s].shader_sha1));
memcpy(stages[s].shader_blake3, retained_shaders->stages[s].shader_blake3, sizeof(stages[s].shader_blake3));
memcpy(&stages[s].key, &retained_shaders->stages[s].key, sizeof(stages[s].key));
radv_shader_layout_init(&lib->layout, s, &stages[s].layout);
@ -3099,7 +3099,7 @@ radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_
if (stage->stage == MESA_SHADER_NONE)
continue;
_mesa_blake3_update(&ctx, stage->shader_sha1, sizeof(stage->shader_sha1));
_mesa_blake3_update(&ctx, stage->shader_blake3, sizeof(stage->shader_blake3));
_mesa_blake3_update(&ctx, &stage->key, sizeof(stage->key));
}
}

2
src/amd/vulkan/radv_pipeline_graphics.h
View file

@ -169,7 +169,7 @@ struct radv_retained_shaders {
struct {
void *serialized_nir;
size_t serialized_nir_size;
unsigned char shader_sha1[BLAKE3_KEY_LEN];
unsigned char shader_blake3[BLAKE3_KEY_LEN];
struct radv_shader_stage_key key;
} stages[MESA_VULKAN_SHADER_STAGES];
};

12
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -35,11 +35,11 @@ struct rt_handle_hash_entry {
};
static uint32_t
handle_from_stages(struct radv_device *device, const unsigned char *shader_sha1, bool replay_namespace)
handle_from_stages(struct radv_device *device, const unsigned char *shader_blake3, bool replay_namespace)
{
uint32_t ret;
memcpy(&ret, shader_sha1, sizeof(ret));
memcpy(&ret, shader_blake3, sizeof(ret));
/* Leave the low half for resume shaders etc. */
ret |= 1u << 31;
@ -56,7 +56,7 @@ handle_from_stages(struct radv_device *device, const unsigned char *shader_sha1,
if (!he)
break;
if (memcmp(he->data, shader_sha1, BLAKE3_KEY_LEN) == 0)
if (memcmp(he->data, shader_blake3, BLAKE3_KEY_LEN) == 0)
break;
++ret;
@ -65,7 +65,7 @@ handle_from_stages(struct radv_device *device, const unsigned char *shader_sha1,
if (!he) {
struct rt_handle_hash_entry *e = ralloc(device->rt_handles, struct rt_handle_hash_entry);
e->key = ret;
memcpy(e->hash, shader_sha1, BLAKE3_KEY_LEN);
memcpy(e->hash, shader_blake3, BLAKE3_KEY_LEN);
_mesa_hash_table_insert(device->rt_handles, &e->key, &e->hash);
}
@ -312,7 +312,7 @@ radv_init_rt_stage_hashes(const struct radv_device *device, VkPipelineCreateFlag
if (header->is_traversal_shader)
continue;
memcpy(stages[i].blake3, header->stage_sha1, BLAKE3_KEY_LEN);
memcpy(stages[i].blake3, header->stage_blake3, BLAKE3_KEY_LEN);
}
} else {
for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) {
@ -1275,7 +1275,7 @@ radv_ray_tracing_pipeline_import_binary(struct radv_device *device, struct radv_
if (header->has_nir) {
nir_shader *nir = nir_deserialize(NULL, NULL, &blob);
pipeline->stages[i].nir = radv_pipeline_cache_nir_to_handle(device, NULL, nir, header->stage_sha1, false);
pipeline->stages[i].nir = radv_pipeline_cache_nir_to_handle(device, NULL, nir, header->stage_blake3, false);
ralloc_free(nir);
if (!pipeline->stages[i].nir)

2
src/amd/vulkan/radv_pipeline_rt.h
View file

@ -133,7 +133,7 @@ struct radv_ray_tracing_binary_header {
uint32_t is_traversal_shader : 1;
uint32_t has_shader : 1;
uint32_t has_nir : 1;
uint8_t stage_sha1[BLAKE3_KEY_LEN];
uint8_t stage_blake3[BLAKE3_KEY_LEN];
uint32_t stack_size;
struct radv_ray_tracing_stage_info stage_info;
};

2
src/amd/vulkan/radv_shader.h
View file

@ -277,7 +277,7 @@ struct radv_shader_stage {
const char *entrypoint;
const VkSpecializationInfo *spec_info;
unsigned char shader_sha1[BLAKE3_KEY_LEN];
unsigned char shader_blake3[BLAKE3_KEY_LEN];
nir_shader *nir;
nir_shader *gs_copy_shader;

10
src/amd/vulkan/radv_shader_object.c
View file

@ -250,13 +250,13 @@ static VkResult
radv_shader_object_init_binary(struct radv_device *device, struct blob_reader *blob, struct radv_shader **shader_out,
struct radv_shader_binary **binary_out)
{
const char *binary_sha1 = blob_read_bytes(blob, BLAKE3_KEY_LEN);
const char *binary_blake3 = blob_read_bytes(blob, BLAKE3_KEY_LEN);
const uint32_t binary_size = blob_read_uint32(blob);
const struct radv_shader_binary *binary = blob_read_bytes(blob, binary_size);
unsigned char blake3[BLAKE3_KEY_LEN];
_mesa_blake3_compute(binary, binary->total_size, blake3);
if (memcmp(blake3, binary_sha1, BLAKE3_KEY_LEN))
if (memcmp(blake3, binary_blake3, BLAKE3_KEY_LEN))
return VK_ERROR_INCOMPATIBLE_SHADER_BINARY_EXT;
*shader_out = radv_shader_create(device, NULL, binary, true);
@ -647,14 +647,14 @@ radv_get_shader_object_size(const struct radv_shader_object *shader_obj)
static void
radv_write_shader_binary(struct blob *blob, const struct radv_shader_binary *binary)
{
unsigned char binary_sha1[BLAKE3_KEY_LEN];
unsigned char binary_blake3[BLAKE3_KEY_LEN];
blob_write_uint32(blob, !!binary);
if (binary) {
_mesa_blake3_compute(binary, binary->total_size, binary_sha1);
_mesa_blake3_compute(binary, binary->total_size, binary_blake3);
blob_write_bytes(blob, binary_sha1, sizeof(binary_sha1));
blob_write_bytes(blob, binary_blake3, sizeof(binary_blake3));
blob_write_uint32(blob, binary->total_size);
blob_write_bytes(blob, binary, binary->total_size);
}

18
src/broadcom/vulkan/v3dv_pipeline.c
View file

@ -55,7 +55,7 @@ pipeline_compute_blake3_from_nir(struct v3dv_pipeline_stage *p_stage)
.stage = mesa_to_vk_shader_stage(p_stage->nir->info.stage),
};
vk_pipeline_hash_shader_stage(0, &info, NULL, p_stage->shader_sha1);
vk_pipeline_hash_shader_stage(0, &info, NULL, p_stage->shader_blake3);
}
void
@ -1442,7 +1442,7 @@ pipeline_stage_create_binning(const struct v3dv_pipeline_stage *src,
p_stage->spec_info = src->spec_info;
p_stage->feedback = (VkPipelineCreationFeedback) { 0 };
p_stage->robustness = src->robustness;
memcpy(p_stage->shader_sha1, src->shader_sha1, BLAKE3_KEY_LEN);
memcpy(p_stage->shader_blake3, src->shader_blake3, BLAKE3_KEY_LEN);
return p_stage;
}
@ -1539,7 +1539,7 @@ pipeline_hash_graphics(const struct v3dv_pipeline *pipeline,
assert(stage != BROADCOM_SHADER_COMPUTE);
_mesa_blake3_update(&ctx, p_stage->shader_sha1, sizeof(p_stage->shader_sha1));
_mesa_blake3_update(&ctx, p_stage->shader_blake3, sizeof(p_stage->shader_blake3));
}
_mesa_blake3_update(&ctx, key, sizeof(struct v3dv_pipeline_key));
@ -1563,7 +1563,7 @@ pipeline_hash_compute(const struct v3dv_pipeline *pipeline,
struct v3dv_pipeline_stage *p_stage =
pipeline->stages[BROADCOM_SHADER_COMPUTE];
_mesa_blake3_update(&ctx, p_stage->shader_sha1, sizeof(p_stage->shader_sha1));
_mesa_blake3_update(&ctx, p_stage->shader_blake3, sizeof(p_stage->shader_blake3));
_mesa_blake3_update(&ctx, key, sizeof(struct v3dv_pipeline_key));
@ -1843,7 +1843,7 @@ pipeline_stage_get_nir(struct v3dv_pipeline_stage *p_stage,
nir = v3dv_pipeline_cache_search_for_nir(pipeline, cache,
nir_options,
p_stage->shader_sha1);
p_stage->shader_blake3);
if (nir) {
assert(nir->info.stage == broadcom_shader_stage_to_gl(p_stage->stage));
@ -1865,14 +1865,14 @@ pipeline_stage_get_nir(struct v3dv_pipeline_stage *p_stage,
&pipeline->device->default_pipeline_cache;
v3dv_pipeline_cache_upload_nir(pipeline, cache, nir,
p_stage->shader_sha1);
p_stage->shader_blake3);
/* Ensure that the variant is on the default cache, as cmd_buffer could
* need to change the current variant
*/
if (default_cache != cache) {
v3dv_pipeline_cache_upload_nir(pipeline, default_cache, nir,
p_stage->shader_sha1);
p_stage->shader_blake3);
}
p_stage->feedback.duration += os_time_get_nano() - stage_start;
@ -2468,7 +2468,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
vk_pipeline_hash_shader_stage(pipeline->flags,
&pCreateInfo->pStages[i],
&p_stage->robustness,
p_stage->shader_sha1);
p_stage->shader_blake3);
pipeline->active_stages |= sinfo->stage;
@ -3182,7 +3182,7 @@ pipeline_compile_compute(struct v3dv_pipeline *pipeline,
vk_pipeline_hash_shader_stage(pipeline->flags,
&info->stage,
&p_stage->robustness,
p_stage->shader_sha1);
p_stage->shader_blake3);
p_stage->nir = NULL;

2
src/broadcom/vulkan/v3dv_private.h
View file

@ -1925,7 +1925,7 @@ struct v3dv_pipeline_stage {
nir_shader *nir;
/* The following is the combined hash of module+entrypoint+spec_info+nir */
unsigned char shader_sha1[BLAKE3_KEY_LEN];
unsigned char shader_blake3[BLAKE3_KEY_LEN];
/** A name for this program, so you can track it in shader-db output. */
uint32_t program_id;

10
src/compiler/glsl/glsl_parser_extras.cpp
View file

@ -2334,11 +2334,11 @@ can_skip_compile(struct gl_context *ctx, struct gl_shader *shader,
if (ctx->Cache) {
char buf[BLAKE3_HEX_LEN];
disk_cache_compute_key(ctx->Cache, source, strlen(source),
shader->disk_cache_sha1);
if (disk_cache_has_key(ctx->Cache, shader->disk_cache_sha1)) {
shader->disk_cache_blake3);
if (disk_cache_has_key(ctx->Cache, shader->disk_cache_blake3)) {
/* We've seen this shader before and know it compiles */
if (ctx->_Shader->Flags & GLSL_CACHE_INFO) {
_mesa_blake3_format(buf, shader->disk_cache_sha1);
_mesa_blake3_format(buf, shader->disk_cache_blake3);
fprintf(stderr, "deferring compile of shader: %s\n", buf);
}
shader->CompileStatus = COMPILE_SKIPPED;
@ -2545,9 +2545,9 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader,
if (ctx->Cache && shader->CompileStatus == COMPILE_SUCCESS) {
char blake3_buf[BLAKE3_HEX_LEN];
disk_cache_put_key(ctx->Cache, shader->disk_cache_sha1);
disk_cache_put_key(ctx->Cache, shader->disk_cache_blake3);
if (ctx->_Shader->Flags & GLSL_CACHE_INFO) {
_mesa_blake3_format(blake3_buf, shader->disk_cache_sha1);
_mesa_blake3_format(blake3_buf, shader->disk_cache_blake3);
fprintf(stderr, "marking shader: %s\n", blake3_buf);
}
}

6
src/compiler/glsl/shader_cache.cpp
View file

@ -121,7 +121,7 @@ shader_cache_write_program_metadata(struct gl_context *ctx,
goto fail;
for (unsigned i = 0; i < prog->NumShaders; i++) {
memcpy(cache_item_metadata.keys[i], prog->Shaders[i]->disk_cache_sha1,
memcpy(cache_item_metadata.keys[i], prog->Shaders[i]->disk_cache_blake3,
sizeof(cache_key));
}
@ -196,12 +196,12 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
* include them as an input to blake3 creation.
*/
char sha1buf[BLAKE3_HEX_LEN];
_mesa_blake3_format(sha1buf, ctx->Const.dri_config_options_sha1);
_mesa_blake3_format(sha1buf, ctx->Const.dri_config_options_blake3);
ralloc_strcat(&buf, sha1buf);
for (unsigned i = 0; i < prog->NumShaders; i++) {
struct gl_shader *sh = prog->Shaders[i];
_mesa_blake3_format(sha1buf, sh->disk_cache_sha1);
_mesa_blake3_format(sha1buf, sh->disk_cache_blake3);
ralloc_asprintf_append(&buf, "%s: %s\n",
_mesa_shader_stage_to_abbrev(sh->Stage), sha1buf);
}

10
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -8036,11 +8036,11 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
trace_start_draw(
&cmd->rp_trace, &cmd->draw_cs, cmd, draw_count,
cmd->state.program.stage_sha1[MESA_SHADER_VERTEX],
cmd->state.program.stage_sha1[MESA_SHADER_TESS_CTRL],
cmd->state.program.stage_sha1[MESA_SHADER_TESS_EVAL],
cmd->state.program.stage_sha1[MESA_SHADER_GEOMETRY],
cmd->state.program.stage_sha1[MESA_SHADER_FRAGMENT]);
cmd->state.program.stage_blake3[MESA_SHADER_VERTEX],
cmd->state.program.stage_blake3[MESA_SHADER_TESS_CTRL],
cmd->state.program.stage_blake3[MESA_SHADER_TESS_EVAL],
cmd->state.program.stage_blake3[MESA_SHADER_GEOMETRY],
cmd->state.program.stage_blake3[MESA_SHADER_FRAGMENT]);
/* Emit state first, because it's needed for bandwidth calculations */
uint32_t dynamic_draw_state_dirty = 0;

38
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -1943,29 +1943,29 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
!builder->rasterizer_discard && msaa_info && msaa_info->sampleShadingEnable;
}
unsigned char pipeline_sha1[BLAKE3_KEY_LEN];
tu_hash_shaders(pipeline_sha1, builder->create_flags, stage_infos, nir,
unsigned char pipeline_blake3[BLAKE3_KEY_LEN];
tu_hash_shaders(pipeline_blake3, builder->create_flags, stage_infos, nir,
&builder->layout, keys, builder->state);
unsigned char nir_sha1[BLAKE3_KEY_LEN + 1];
memcpy(nir_sha1, pipeline_sha1, sizeof(pipeline_sha1));
nir_sha1[BLAKE3_KEY_LEN] = 'N';
unsigned char nir_blake3[BLAKE3_KEY_LEN + 1];
memcpy(nir_blake3, pipeline_blake3, sizeof(pipeline_blake3));
nir_blake3[BLAKE3_KEY_LEN] = 'N';
if (!executable_info) {
cache_hit = true;
bool application_cache_hit = false;
unsigned char shader_sha1[BLAKE3_KEY_LEN + 1];
memcpy(shader_sha1, pipeline_sha1, sizeof(pipeline_sha1));
unsigned char shader_blake3[BLAKE3_KEY_LEN + 1];
memcpy(shader_blake3, pipeline_blake3, sizeof(pipeline_blake3));
for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < ARRAY_SIZE(nir);
stage = (mesa_shader_stage) (stage + 1)) {
if (stage_infos[stage] || nir[stage]) {
bool shader_application_cache_hit;
shader_sha1[BLAKE3_KEY_LEN] = (unsigned char) stage;
shader_blake3[BLAKE3_KEY_LEN] = (unsigned char) stage;
shaders[stage] =
tu_pipeline_cache_lookup(builder->cache, &shader_sha1,
sizeof(shader_sha1),
tu_pipeline_cache_lookup(builder->cache, &shader_blake3,
sizeof(shader_blake3),
&shader_application_cache_hit);
if (!shaders[stage]) {
cache_hit = false;
@ -1984,8 +1984,8 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
VK_PIPELINE_CREATE_2_RETAIN_LINK_TIME_OPTIMIZATION_INFO_BIT_EXT)) {
bool nir_application_cache_hit = false;
nir_shaders =
tu_nir_cache_lookup(builder->cache, &nir_sha1,
sizeof(nir_sha1),
tu_nir_cache_lookup(builder->cache, &nir_blake3,
sizeof(nir_blake3),
&nir_application_cache_hit);
application_cache_hit &= nir_application_cache_hit;
@ -2010,7 +2010,7 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
nir,
keys,
&builder->layout,
pipeline_sha1,
pipeline_blake3,
shaders,
executable_info ? nir_initial_disasm : NULL,
pipeline->executables_mem_ctx,
@ -2022,7 +2022,7 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
if (retain_nir) {
nir_shaders =
tu_nir_shaders_init(builder->device, &nir_sha1, sizeof(nir_sha1));
tu_nir_shaders_init(builder->device, &nir_blake3, sizeof(nir_blake3));
for (mesa_shader_stage stage = MESA_SHADER_VERTEX;
stage < ARRAY_SIZE(nir); stage = (mesa_shader_stage) (stage + 1)) {
if (!post_link_nir[stage])
@ -2336,7 +2336,7 @@ tu_emit_program_state(struct tu_cs *sub_cs,
}
if (variants[stage]) {
memcpy(prog->stage_sha1[stage], variants[stage]->blake3_str,
memcpy(prog->stage_blake3[stage], variants[stage]->blake3_str,
sizeof(variants[stage]->blake3_str));
}
}
@ -4933,8 +4933,8 @@ tu_compute_pipeline_create(VkDevice device,
void *pipeline_mem_ctx = ralloc_context(NULL);
unsigned char pipeline_sha1[BLAKE3_KEY_LEN];
tu_hash_compute(pipeline_sha1, flags, stage_info, layout, &key);
unsigned char pipeline_blake3[BLAKE3_KEY_LEN];
tu_hash_compute(pipeline_blake3, flags, stage_info, layout, &key);
struct tu_shader *shader = NULL;
@ -4945,7 +4945,7 @@ tu_compute_pipeline_create(VkDevice device,
if (!executable_info) {
shader =
tu_pipeline_cache_lookup(cache, pipeline_sha1, sizeof(pipeline_sha1),
tu_pipeline_cache_lookup(cache, pipeline_blake3, sizeof(pipeline_blake3),
&application_cache_hit);
}
@ -4972,7 +4972,7 @@ tu_compute_pipeline_create(VkDevice device,
nir_shader_as_str(nir, pipeline->base.executables_mem_ctx) : NULL;
result = tu_shader_create(dev, &shader, nir, &key, &ir3_key,
pipeline_sha1, sizeof(pipeline_sha1), layout,
pipeline_blake3, sizeof(pipeline_blake3), layout,
executable_info);
if (!shader) {
goto fail;

2
src/freedreno/vulkan/tu_pipeline.h
View file

@ -110,7 +110,7 @@ struct tu_program_state
struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
char stage_sha1[MESA_SHADER_STAGES][BLAKE3_HEX_LEN];
char stage_blake3[MESA_SHADER_STAGES][BLAKE3_HEX_LEN];
unsigned dynamic_descriptor_offsets[MAX_SETS];

10
src/freedreno/vulkan/tu_shader.cc
View file

@ -3339,7 +3339,7 @@ tu_compile_shaders(struct tu_device *device,
nir_shader **nir,
const struct tu_shader_key *keys,
struct tu_pipeline_layout *layout,
const unsigned char *pipeline_sha1,
const unsigned char *pipeline_blake3,
struct tu_shader **shaders,
char **nir_initial_disasm,
void *nir_initial_disasm_mem_ctx,
@ -3453,13 +3453,13 @@ tu_compile_shaders(struct tu_device *device,
int64_t stage_start = os_time_get_nano();
unsigned char shader_sha1[BLAKE3_KEY_LEN + 1];
memcpy(shader_sha1, pipeline_sha1, BLAKE3_KEY_LEN);
shader_sha1[BLAKE3_KEY_LEN] = (unsigned char) stage;
unsigned char shader_blake3[BLAKE3_KEY_LEN + 1];
memcpy(shader_blake3, pipeline_blake3, BLAKE3_KEY_LEN);
shader_blake3[BLAKE3_KEY_LEN] = (unsigned char) stage;
result = tu_shader_create(device,
&shaders[stage], nir[stage], &keys[stage],
&ir3_key, shader_sha1, sizeof(shader_sha1),
&ir3_key, shader_blake3, sizeof(shader_blake3),
layout, !!nir_initial_disasm);
if (result != VK_SUCCESS) {
goto fail;

2
src/freedreno/vulkan/tu_shader.h
View file

@ -220,7 +220,7 @@ tu_compile_shaders(struct tu_device *device,
nir_shader **nir,
const struct tu_shader_key *keys,
struct tu_pipeline_layout *layout,
const unsigned char *pipeline_sha1,
const unsigned char *pipeline_blake3,
struct tu_shader **shaders,
char **nir_initial_disasm,
void *nir_initial_disasm_mem_ctx,

2
src/gallium/auxiliary/util/u_driconf.c
View file

@ -80,5 +80,5 @@ u_driconf_fill_st_options(struct st_config_options *options,
query_bool_option(allow_multisampled_copyteximage);
query_bool_option(vertex_program_default_out);
driComputeOptionsSha1(optionCache, options->config_options_sha1);
driComputeOptionsSha1(optionCache, options->config_options_blake3);
}

6
src/gallium/drivers/asahi/agx_disk_cache.c
View file

@ -31,8 +31,8 @@ agx_disk_cache_compute_key(struct disk_cache *cache,
const union asahi_shader_key *shader_key,
cache_key cache_key)
{
uint8_t data[sizeof(uncompiled->nir_sha1) + sizeof(*shader_key)];
int hash_size = sizeof(uncompiled->nir_sha1);
uint8_t data[sizeof(uncompiled->nir_blake3) + sizeof(*shader_key)];
int hash_size = sizeof(uncompiled->nir_blake3);
int key_size;
if (uncompiled->type == MESA_SHADER_VERTEX ||
uncompiled->type == MESA_SHADER_TESS_EVAL)
@ -42,7 +42,7 @@ agx_disk_cache_compute_key(struct disk_cache *cache,
else
key_size = 0;
memcpy(data, uncompiled->nir_sha1, hash_size);
memcpy(data, uncompiled->nir_blake3, hash_size);
if (key_size)
memcpy(data + hash_size, shader_key, key_size);

2
src/gallium/drivers/asahi/agx_state.c
View file

@ -1863,7 +1863,7 @@ agx_shader_initialize(struct agx_device *dev, struct agx_uncompiled_shader *so,
blob_init(&so->serialized_nir);
nir_serialize(&so->serialized_nir, nir, true);
_mesa_blake3_compute(so->serialized_nir.data, so->serialized_nir.size,
so->nir_sha1);
so->nir_blake3);
so->has_xfb_info = (nir->xfb_info != NULL);

2
src/gallium/drivers/asahi/agx_state.h
View file

@ -270,7 +270,7 @@ struct agx_uncompiled_shader {
mesa_shader_stage type;
struct blob early_serialized_nir;
struct blob serialized_nir;
uint8_t nir_sha1[BLAKE3_KEY_LEN];
uint8_t nir_blake3[BLAKE3_KEY_LEN];
struct {
uint64_t inputs_flat_shaded;

2
src/gallium/drivers/crocus/crocus_context.h
View file

@ -309,7 +309,7 @@ struct crocus_uncompiled_shader {
struct pipe_stream_output_info stream_output;
/* A BLAKE3 of the serialized NIR for the disk cache. */
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
unsigned program_id;

8
src/gallium/drivers/crocus/crocus_disk_cache.c
View file

@ -59,11 +59,11 @@ crocus_disk_cache_compute_key(struct disk_cache *cache,
memcpy(&prog_key, orig_prog_key, prog_key_size);
prog_key.base.program_string_id = 0;
uint8_t data[sizeof(prog_key) + sizeof(ish->nir_sha1)];
uint32_t data_size = prog_key_size + sizeof(ish->nir_sha1);
uint8_t data[sizeof(prog_key) + sizeof(ish->nir_blake3)];
uint32_t data_size = prog_key_size + sizeof(ish->nir_blake3);
memcpy(data, ish->nir_sha1, sizeof(ish->nir_sha1));
memcpy(data + sizeof(ish->nir_sha1), &prog_key, prog_key_size);
memcpy(data, ish->nir_blake3, sizeof(ish->nir_blake3));
memcpy(data + sizeof(ish->nir_blake3), &prog_key, prog_key_size);
disk_cache_compute_key(cache, data, data_size, cache_key);
}

2
src/gallium/drivers/crocus/crocus_program.c
View file

@ -2711,7 +2711,7 @@ crocus_create_uncompiled_shader(struct pipe_context *ctx,
struct blob blob;
blob_init(&blob);
nir_serialize(&blob, nir, true);
_mesa_blake3_compute(blob.data, blob.size, ish->nir_sha1);
_mesa_blake3_compute(blob.data, blob.size, ish->nir_blake3);
blob_finish(&blob);
}

2
src/gallium/drivers/iris/iris_context.h
View file

@ -546,7 +546,7 @@ struct iris_uncompiled_shader {
struct pipe_stream_output_info stream_output;
/* A BLAKE3 of the serialized NIR for the disk cache. */
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
/* Hash value based on shader source program */
unsigned source_hash;

10
src/gallium/drivers/iris/iris_disk_cache.c
View file

@ -44,11 +44,11 @@ iris_disk_cache_compute_key(struct disk_cache *cache,
memcpy(&prog_key, orig_prog_key, prog_key_size);
prog_key.base.program_string_id = 0;
uint8_t data[sizeof(prog_key) + sizeof(ish->nir_sha1)];
uint32_t data_size = prog_key_size + sizeof(ish->nir_sha1);
uint8_t data[sizeof(prog_key) + sizeof(ish->nir_blake3)];
uint32_t data_size = prog_key_size + sizeof(ish->nir_blake3);
memcpy(data, ish->nir_sha1, sizeof(ish->nir_sha1));
memcpy(data + sizeof(ish->nir_sha1), &prog_key, prog_key_size);
memcpy(data, ish->nir_blake3, sizeof(ish->nir_blake3));
memcpy(data + sizeof(ish->nir_blake3), &prog_key, prog_key_size);
disk_cache_compute_key(cache, data, data_size, cache_key);
}
@ -336,7 +336,7 @@ iris_disk_cache_init(struct iris_screen *screen)
if (screen->brw) {
char device_info_sha[BLAKE3_HEX_LEN];
brw_device_sha1(device_info_sha, screen->devinfo);
brw_device_blake3(device_info_sha, screen->devinfo);
memcpy(renderer, "iris_", 5);
memcpy(renderer + 5, device_info_sha, 40);
} else {

2
src/gallium/drivers/iris/iris_program.c
View file

@ -3380,7 +3380,7 @@ iris_create_uncompiled_shader(struct iris_screen *screen,
struct blob blob;
blob_init(&blob);
nir_serialize(&blob, nir, true);
_mesa_blake3_compute(blob.data, blob.size, ish->nir_sha1);
_mesa_blake3_compute(blob.data, blob.size, ish->nir_blake3);
blob_finish(&blob);
}

8
src/gallium/drivers/lima/lima_context.h
View file

@ -57,11 +57,11 @@ struct lima_fs_compiled_shader {
struct lima_fs_uncompiled_shader {
struct pipe_shader_state base;
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
};
struct lima_fs_key {
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
struct {
enum pipe_format format;
uint8_t swizzle[4];
@ -98,11 +98,11 @@ struct lima_vs_compiled_shader {
struct lima_vs_uncompiled_shader {
struct pipe_shader_state base;
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
};
struct lima_vs_key {
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
};
struct lima_rasterizer_state {

20
src/gallium/drivers/lima/lima_program.c
View file

@ -467,14 +467,14 @@ lima_create_fs_state(struct pipe_context *pctx,
struct blob blob;
blob_init(&blob);
nir_serialize(&blob, nir, true);
_mesa_blake3_compute(blob.data, blob.size, so->nir_sha1);
_mesa_blake3_compute(blob.data, blob.size, so->nir_blake3);
blob_finish(&blob);
if (lima_debug & LIMA_DEBUG_PRECOMPILE) {
/* Trigger initial compilation with default settings */
struct lima_fs_key key;
memset(&key, 0, sizeof(key));
memcpy(key.nir_sha1, so->nir_sha1, sizeof(so->nir_sha1));
memcpy(key.nir_blake3, so->nir_blake3, sizeof(so->nir_blake3));
for (int i = 0; i < ARRAY_SIZE(key.tex); i++) {
for (int j = 0; j < 4; j++)
key.tex[i].swizzle[j] = j;
@ -502,7 +502,7 @@ lima_delete_fs_state(struct pipe_context *pctx, void *hwcso)
hash_table_foreach(ctx->fs_cache, entry) {
const struct lima_fs_key *key = entry->key;
if (!memcmp(key->nir_sha1, so->nir_sha1, sizeof(so->nir_sha1))) {
if (!memcmp(key->nir_blake3, so->nir_blake3, sizeof(so->nir_blake3))) {
struct lima_fs_compiled_shader *fs = entry->data;
_mesa_hash_table_remove(ctx->fs_cache, entry);
if (fs->bo)
@ -617,8 +617,8 @@ lima_update_vs_state(struct lima_context *ctx)
struct lima_vs_key local_key;
struct lima_vs_key *key = &local_key;
memset(key, 0, sizeof(*key));
memcpy(key->nir_sha1, ctx->uncomp_vs->nir_sha1,
sizeof(ctx->uncomp_vs->nir_sha1));
memcpy(key->nir_blake3, ctx->uncomp_vs->nir_blake3,
sizeof(ctx->uncomp_vs->nir_blake3));
struct lima_vs_compiled_shader *old_vs = ctx->vs;
struct lima_vs_compiled_shader *vs = lima_get_compiled_vs(ctx,
@ -647,8 +647,8 @@ lima_update_fs_state(struct lima_context *ctx)
struct lima_fs_key local_key;
struct lima_fs_key *key = &local_key;
memset(key, 0, sizeof(*key));
memcpy(key->nir_sha1, ctx->uncomp_fs->nir_sha1,
sizeof(ctx->uncomp_fs->nir_sha1));
memcpy(key->nir_blake3, ctx->uncomp_fs->nir_blake3,
sizeof(ctx->uncomp_fs->nir_blake3));
if (ctx->framebuffer.base.cbufs[0].texture)
key->color_format = ctx->framebuffer.base.cbufs[0].format;
@ -720,14 +720,14 @@ lima_create_vs_state(struct pipe_context *pctx,
struct blob blob;
blob_init(&blob);
nir_serialize(&blob, nir, true);
_mesa_blake3_compute(blob.data, blob.size, so->nir_sha1);
_mesa_blake3_compute(blob.data, blob.size, so->nir_blake3);
blob_finish(&blob);
if (lima_debug & LIMA_DEBUG_PRECOMPILE) {
/* Trigger initial compilation with default settings */
struct lima_vs_key key;
memset(&key, 0, sizeof(key));
memcpy(key.nir_sha1, so->nir_sha1, sizeof(so->nir_sha1));
memcpy(key.nir_blake3, so->nir_blake3, sizeof(so->nir_blake3));
lima_get_compiled_vs(ctx, so, &key);
}
@ -751,7 +751,7 @@ lima_delete_vs_state(struct pipe_context *pctx, void *hwcso)
hash_table_foreach(ctx->vs_cache, entry) {
const struct lima_vs_key *key = entry->key;
if (!memcmp(key->nir_sha1, so->nir_sha1, sizeof(so->nir_sha1))) {
if (!memcmp(key->nir_blake3, so->nir_blake3, sizeof(so->nir_blake3))) {
struct lima_vs_compiled_shader *vs = entry->data;
_mesa_hash_table_remove(ctx->vs_cache, entry);
if (vs->bo)

2
src/gallium/drivers/panfrost/pan_context.h
View file

@ -397,7 +397,7 @@ struct panfrost_uncompiled_shader {
const nir_shader *nir;
/* A BLAKE3 of the serialized NIR for the disk cache. */
unsigned char nir_sha1[BLAKE3_KEY_LEN];
unsigned char nir_blake3[BLAKE3_KEY_LEN];
/* Stream output information */
struct pipe_stream_output_info stream_output;

6
src/gallium/drivers/panfrost/pan_disk_cache.c
View file

@ -34,10 +34,10 @@ panfrost_disk_cache_compute_key(
const struct panfrost_uncompiled_shader *uncompiled,
const struct panfrost_shader_key *shader_key, cache_key cache_key)
{
uint8_t data[sizeof(uncompiled->nir_sha1) + sizeof(*shader_key)];
uint8_t data[sizeof(uncompiled->nir_blake3) + sizeof(*shader_key)];
memcpy(data, uncompiled->nir_sha1, sizeof(uncompiled->nir_sha1));
memcpy(data + sizeof(uncompiled->nir_sha1), shader_key, sizeof(*shader_key));
memcpy(data, uncompiled->nir_blake3, sizeof(uncompiled->nir_blake3));
memcpy(data + sizeof(uncompiled->nir_blake3), shader_key, sizeof(*shader_key));
disk_cache_compute_key(cache, data, sizeof(data), cache_key);
}

2
src/gallium/drivers/panfrost/pan_shader.c
View file

@ -39,7 +39,7 @@ panfrost_alloc_shader(const nir_shader *nir)
struct blob blob;
blob_init(&blob);
nir_serialize(&blob, nir, true);
_mesa_blake3_compute(blob.data, blob.size, so->nir_sha1);
_mesa_blake3_compute(blob.data, blob.size, so->nir_blake3);
blob_finish(&blob);
return so;

2
src/gallium/include/frontend/api.h
View file

@ -210,7 +210,7 @@ struct st_config_options
bool allow_multisampled_copyteximage;
bool vertex_program_default_out;
unsigned char config_options_sha1[BLAKE3_KEY_LEN];
unsigned char config_options_blake3[BLAKE3_KEY_LEN];
};
struct pipe_frontend_screen;

2
src/intel/compiler/brw/brw_compiler.c
View file

@ -280,7 +280,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
}
void
brw_device_sha1(char *hex,
brw_device_blake3(char *hex,
const struct intel_device_info *devinfo) {
blake3_hasher ctx;
_mesa_blake3_init(&ctx);

2
src/intel/compiler/brw/brw_compiler.h
View file

@ -1294,7 +1294,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler);
* affect shader compilation.
*/
void
brw_device_sha1(char *hex, const struct intel_device_info *devinfo);
brw_device_blake3(char *hex, const struct intel_device_info *devinfo);
/* For callers computing their own UUID or hash. Hashes all device
* information fields that could affect shader compilation into the provided

10
src/intel/dev/intel_device_info_serialize_gen_c.py
View file

@ -149,12 +149,12 @@ intel_device_info_from_json(const char *path,
struct intel_device_info *devinfo) {
JSON_Value *root = json_parse_file(path);
JSON_Object *obj = json_object(root);
const char *devinfo_type_sha1 = "${checksum}";
const char *devinfo_type_blake3 = "${checksum}";
/* verify that json was generated with a compatible driver */
if (strncmp(devinfo_type_sha1,
json_object_get_string(obj, "devinfo_type_sha1"),
strlen(devinfo_type_sha1)))
if (strncmp(devinfo_type_blake3,
json_object_get_string(obj, "devinfo_type_blake3"),
strlen(devinfo_type_blake3)))
return false;
load_intel_device_info(obj, devinfo);
@ -174,7 +174,7 @@ intel_device_info_dump_json(const struct intel_device_info *devinfo) {
* an incompatible driver
*/
JSON_Object *obj = json_object(root);
json_object_set_string(obj, "devinfo_type_sha1", "${checksum}");
json_object_set_string(obj, "devinfo_type_blake3", "${checksum}");
return root;
}

4
src/intel/tools/intel_dev_info.c
View file

@ -282,8 +282,8 @@ main(int argc, char *argv[])
if (devinfo.ver >= 9) {
JSON_Object *obj = json_object(json);
char device_info_sha[BLAKE3_HEX_LEN];
brw_device_sha1(device_info_sha, &devinfo);
json_object_set_string(obj, "shader_cache_sha1", device_info_sha);
brw_device_blake3(device_info_sha, &devinfo);
json_object_set_string(obj, "shader_cache_blake3", device_info_sha);
}
char *pretty_string = json_serialize_to_string_pretty(json);

18
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -435,25 +435,25 @@ set_dirty_for_bind_map(struct anv_cmd_buffer *cmd_buffer,
mesa_shader_stage stage,
const struct anv_pipeline_bind_map *map)
{
assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_sha1s));
if (mem_update(cmd_buffer->state.surface_sha1s[stage],
map->surface_sha1, sizeof(map->surface_sha1))) {
assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_blake3s));
if (mem_update(cmd_buffer->state.surface_blake3s[stage],
map->surface_blake3, sizeof(map->surface_blake3))) {
anv_cmd_buffer_dirty_descriptors(cmd_buffer,
mesa_to_vk_shader_stage(stage),
"shader surfaces change");
}
assert(stage < ARRAY_SIZE(cmd_buffer->state.sampler_sha1s));
if (mem_update(cmd_buffer->state.sampler_sha1s[stage],
map->sampler_sha1, sizeof(map->sampler_sha1))) {
assert(stage < ARRAY_SIZE(cmd_buffer->state.sampler_blake3s));
if (mem_update(cmd_buffer->state.sampler_blake3s[stage],
map->sampler_blake3, sizeof(map->sampler_blake3))) {
anv_cmd_buffer_dirty_descriptors(cmd_buffer,
mesa_to_vk_shader_stage(stage),
"shader samplers change");
}
assert(stage < ARRAY_SIZE(cmd_buffer->state.push_sha1s));
if (mem_update(cmd_buffer->state.push_sha1s[stage],
map->push_sha1, sizeof(map->push_sha1)))
assert(stage < ARRAY_SIZE(cmd_buffer->state.push_blake3s));
if (mem_update(cmd_buffer->state.push_blake3s[stage],
map->push_blake3, sizeof(map->push_blake3)))
cmd_buffer->state.push_constants_dirty |= mesa_to_vk_shader_stage(stage);
}

4
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
View file

@ -2664,9 +2664,9 @@ anv_nir_apply_pipeline_layout(nir_shader *shader,
*/
_mesa_blake3_compute(map->surface_to_descriptor,
map->surface_count * sizeof(struct anv_pipeline_binding),
map->surface_sha1);
map->surface_blake3);
_mesa_blake3_compute(map->sampler_to_descriptor,
map->sampler_count * sizeof(struct anv_pipeline_binding),
map->sampler_sha1);
map->sampler_blake3);
return progress;
}

2
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -769,7 +769,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
*/
_mesa_blake3_compute(map->push_ranges,
sizeof(map->push_ranges),
map->push_sha1);
map->push_blake3);
return progress;
}

12
src/intel/vulkan/anv_private.h
View file

@ -1163,9 +1163,9 @@ enum anv_pipeline_behavior {
#define ANV_INLINE_DWORD_MESH_PROVOKING_VERTEX (UINT8_MAX - 2)
struct anv_pipeline_bind_map {
unsigned char surface_sha1[BLAKE3_KEY_LEN];
unsigned char sampler_sha1[BLAKE3_KEY_LEN];
unsigned char push_sha1[BLAKE3_KEY_LEN];
unsigned char surface_blake3[BLAKE3_KEY_LEN];
unsigned char sampler_blake3[BLAKE3_KEY_LEN];
unsigned char push_blake3[BLAKE3_KEY_LEN];
/* enum anv_descriptor_set_layout_type */
uint16_t layout_type;
@ -4820,9 +4820,9 @@ struct anv_cmd_state {
struct anv_state binding_tables[MESA_VULKAN_SHADER_STAGES];
struct anv_state samplers[MESA_VULKAN_SHADER_STAGES];
unsigned char sampler_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char surface_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char push_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char sampler_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char surface_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char push_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
/* The last auxiliary surface operation (or equivalent operation) provided
* to genX(cmd_buffer_update_color_aux_op).

18
src/intel/vulkan/anv_shader.c
View file

@ -66,9 +66,9 @@ anv_shader_deserialize(struct vk_device *vk_device,
data.push_desc_info.fully_promoted_ubo_descriptors = blob_read_uint32(blob);
data.push_desc_info.push_set_buffer = blob_read_uint8(blob);
blob_copy_bytes(blob, data.bind_map.surface_sha1, sizeof(data.bind_map.surface_sha1));
blob_copy_bytes(blob, data.bind_map.sampler_sha1, sizeof(data.bind_map.sampler_sha1));
blob_copy_bytes(blob, data.bind_map.push_sha1, sizeof(data.bind_map.push_sha1));
blob_copy_bytes(blob, data.bind_map.surface_blake3, sizeof(data.bind_map.surface_blake3));
blob_copy_bytes(blob, data.bind_map.sampler_blake3, sizeof(data.bind_map.sampler_blake3));
blob_copy_bytes(blob, data.bind_map.push_blake3, sizeof(data.bind_map.push_blake3));
data.bind_map.layout_type = blob_read_uint16(blob);
data.bind_map.binding_mask = blob_read_uint16(blob);
data.bind_map.surface_count = blob_read_uint8(blob);
@ -148,12 +148,12 @@ anv_shader_serialize(struct vk_device *device,
blob_write_uint32(blob, shader->push_desc_info.fully_promoted_ubo_descriptors);
blob_write_uint8(blob, shader->push_desc_info.push_set_buffer);
blob_write_bytes(blob, shader->bind_map.surface_sha1,
sizeof(shader->bind_map.surface_sha1));
blob_write_bytes(blob, shader->bind_map.sampler_sha1,
sizeof(shader->bind_map.sampler_sha1));
blob_write_bytes(blob, shader->bind_map.push_sha1,
sizeof(shader->bind_map.push_sha1));
blob_write_bytes(blob, shader->bind_map.surface_blake3,
sizeof(shader->bind_map.surface_blake3));
blob_write_bytes(blob, shader->bind_map.sampler_blake3,
sizeof(shader->bind_map.sampler_blake3));
blob_write_bytes(blob, shader->bind_map.push_blake3,
sizeof(shader->bind_map.push_blake3));
blob_write_uint16(blob, shader->bind_map.layout_type);
blob_write_uint16(blob, shader->bind_map.binding_mask);
blob_write_uint8(blob, shader->bind_map.surface_count);

18
src/intel/vulkan_hasvk/anv_cmd_buffer.c
View file

@ -251,19 +251,19 @@ set_dirty_for_bind_map(struct anv_cmd_buffer *cmd_buffer,
mesa_shader_stage stage,
const struct anv_pipeline_bind_map *map)
{
assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_sha1s));
if (mem_update(cmd_buffer->state.surface_sha1s[stage],
map->surface_sha1, sizeof(map->surface_sha1)))
assert(stage < ARRAY_SIZE(cmd_buffer->state.surface_blake3s));
if (mem_update(cmd_buffer->state.surface_blake3s[stage],
map->surface_blake3, sizeof(map->surface_blake3)))
cmd_buffer->state.descriptors_dirty |= mesa_to_vk_shader_stage(stage);
assert(stage < ARRAY_SIZE(cmd_buffer->state.sampler_sha1s));
if (mem_update(cmd_buffer->state.sampler_sha1s[stage],
map->sampler_sha1, sizeof(map->sampler_sha1)))
assert(stage < ARRAY_SIZE(cmd_buffer->state.sampler_blake3s));
if (mem_update(cmd_buffer->state.sampler_blake3s[stage],
map->sampler_blake3, sizeof(map->sampler_blake3)))
cmd_buffer->state.descriptors_dirty |= mesa_to_vk_shader_stage(stage);
assert(stage < ARRAY_SIZE(cmd_buffer->state.push_sha1s));
if (mem_update(cmd_buffer->state.push_sha1s[stage],
map->push_sha1, sizeof(map->push_sha1)))
assert(stage < ARRAY_SIZE(cmd_buffer->state.push_blake3s));
if (mem_update(cmd_buffer->state.push_blake3s[stage],
map->push_blake3, sizeof(map->push_blake3)))
cmd_buffer->state.push_constants_dirty |= mesa_to_vk_shader_stage(stage);
}

4
src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c
View file

@ -1466,9 +1466,9 @@ anv_nir_apply_pipeline_layout(nir_shader *shader,
*/
_mesa_blake3_compute(map->surface_to_descriptor,
map->surface_count * sizeof(struct anv_pipeline_binding),
map->surface_sha1);
map->surface_blake3);
_mesa_blake3_compute(map->sampler_to_descriptor,
map->sampler_count * sizeof(struct anv_pipeline_binding),
map->sampler_sha1);
map->sampler_blake3);
return true;
}

2
src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c
View file

@ -247,7 +247,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
*/
_mesa_blake3_compute(map->push_ranges,
sizeof(map->push_ranges),
map->push_sha1);
map->push_blake3);
return has_push_intrinsic;
}

18
src/intel/vulkan_hasvk/anv_pipeline.c
View file

@ -337,7 +337,7 @@ struct anv_pipeline_stage {
VkPipelineCreateFlags2KHR pipeline_flags;
const VkPipelineShaderStageCreateInfo *info;
unsigned char shader_sha1[BLAKE3_KEY_LEN];
unsigned char shader_blake3[BLAKE3_KEY_LEN];
union elk_any_prog_key key;
@ -382,8 +382,8 @@ anv_pipeline_hash_graphics(struct anv_graphics_pipeline *pipeline,
for (uint32_t s = 0; s < ANV_GRAPHICS_SHADER_STAGE_COUNT; s++) {
if (stages[s].info) {
_mesa_blake3_update(&ctx, stages[s].shader_sha1,
sizeof(stages[s].shader_sha1));
_mesa_blake3_update(&ctx, stages[s].shader_blake3,
sizeof(stages[s].shader_blake3));
_mesa_blake3_update(&ctx, &stages[s].key, elk_prog_key_size(s));
}
}
@ -411,8 +411,8 @@ anv_pipeline_hash_compute(struct anv_compute_pipeline *pipeline,
const uint8_t afs = device->physical->instance->assume_full_subgroups;
_mesa_blake3_update(&ctx, &afs, sizeof(afs));
_mesa_blake3_update(&ctx, stage->shader_sha1,
sizeof(stage->shader_sha1));
_mesa_blake3_update(&ctx, stage->shader_blake3,
sizeof(stage->shader_blake3));
_mesa_blake3_update(&ctx, &stage->key.cs, sizeof(stage->key.cs));
_mesa_blake3_final(&ctx, blake3_out);
@ -432,7 +432,7 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
nir = anv_device_search_for_nir(pipeline->device, cache,
nir_options,
stage->shader_sha1,
stage->shader_blake3,
mem_ctx);
if (nir) {
assert(nir->info.stage == stage->stage);
@ -443,7 +443,7 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
stage->pipeline_flags, stage->info,
stage->key.base.robust_flags, mem_ctx);
if (nir) {
anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_sha1);
anv_device_upload_nir(pipeline->device, cache, nir, stage->shader_blake3);
return nir;
}
@ -1041,7 +1041,7 @@ anv_graphics_pipeline_init_keys(struct anv_graphics_pipeline *pipeline,
int64_t stage_start = os_time_get_nano();
vk_pipeline_hash_shader_stage(stages[s].pipeline_flags, stages[s].info,
NULL, stages[s].shader_sha1);
NULL, stages[s].shader_blake3);
const struct anv_device *device = pipeline->base.device;
enum elk_robustness_flags robust_flags = anv_device_get_robust_flags(device);
@ -1450,7 +1450,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
},
};
vk_pipeline_hash_shader_stage(stage.pipeline_flags, &info->stage,
NULL, stage.shader_sha1);
NULL, stage.shader_blake3);
struct anv_shader_bin *bin = NULL;

18
src/intel/vulkan_hasvk/anv_pipeline_cache.c
View file

@ -196,12 +196,12 @@ anv_shader_bin_serialize(struct vk_pipeline_cache_object *object,
blob_write_uint32(blob, 0);
}
blob_write_bytes(blob, shader->bind_map.surface_sha1,
sizeof(shader->bind_map.surface_sha1));
blob_write_bytes(blob, shader->bind_map.sampler_sha1,
sizeof(shader->bind_map.sampler_sha1));
blob_write_bytes(blob, shader->bind_map.push_sha1,
sizeof(shader->bind_map.push_sha1));
blob_write_bytes(blob, shader->bind_map.surface_blake3,
sizeof(shader->bind_map.surface_blake3));
blob_write_bytes(blob, shader->bind_map.sampler_blake3,
sizeof(shader->bind_map.sampler_blake3));
blob_write_bytes(blob, shader->bind_map.push_blake3,
sizeof(shader->bind_map.push_blake3));
blob_write_uint32(blob, shader->bind_map.surface_count);
blob_write_uint32(blob, shader->bind_map.sampler_count);
blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
@ -251,9 +251,9 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache,
xfb_info = blob_read_bytes(blob, xfb_size);
struct anv_pipeline_bind_map bind_map;
blob_copy_bytes(blob, bind_map.surface_sha1, sizeof(bind_map.surface_sha1));
blob_copy_bytes(blob, bind_map.sampler_sha1, sizeof(bind_map.sampler_sha1));
blob_copy_bytes(blob, bind_map.push_sha1, sizeof(bind_map.push_sha1));
blob_copy_bytes(blob, bind_map.surface_blake3, sizeof(bind_map.surface_blake3));
blob_copy_bytes(blob, bind_map.sampler_blake3, sizeof(bind_map.sampler_blake3));
blob_copy_bytes(blob, bind_map.push_blake3, sizeof(bind_map.push_blake3));
bind_map.surface_count = blob_read_uint32(blob);
bind_map.sampler_count = blob_read_uint32(blob);
bind_map.surface_to_descriptor = (void *)

12
src/intel/vulkan_hasvk/anv_private.h
View file

@ -2479,9 +2479,9 @@ struct anv_cmd_state {
struct anv_state binding_tables[MESA_VULKAN_SHADER_STAGES];
struct anv_state samplers[MESA_VULKAN_SHADER_STAGES];
unsigned char sampler_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char surface_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char push_sha1s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char sampler_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char surface_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
unsigned char push_blake3s[MESA_VULKAN_SHADER_STAGES][BLAKE3_KEY_LEN];
/**
* Whether or not the gfx8 PMA fix is enabled. We ensure that, at the top
@ -2700,9 +2700,9 @@ struct anv_event {
__tmp &= ~(1 << (stage)))
struct anv_pipeline_bind_map {
unsigned char surface_sha1[BLAKE3_KEY_LEN];
unsigned char sampler_sha1[BLAKE3_KEY_LEN];
unsigned char push_sha1[BLAKE3_KEY_LEN];
unsigned char surface_blake3[BLAKE3_KEY_LEN];
unsigned char sampler_blake3[BLAKE3_KEY_LEN];
unsigned char push_blake3[BLAKE3_KEY_LEN];
uint32_t surface_count;
uint32_t sampler_count;

2
src/mesa/main/consts_exts.h
View file

@ -875,7 +875,7 @@ struct gl_constants
GLuint SparseBufferPageSize;
/** Used as an input for blake3 generation in the on-disk shader cache */
unsigned char *dri_config_options_sha1;
unsigned char *dri_config_options_blake3;
/** When drivers are OK with mapped buffers during draw and other calls. */
bool AllowMappedBuffersDuringExecution;

12
src/mesa/main/program_binary.c
View file

@ -236,10 +236,10 @@ _mesa_get_program_binary(struct gl_context *ctx,
GLenum *binary_format, GLvoid *binary)
{
struct blob blob;
uint8_t driver_sha1[BLAKE3_KEY_LEN];
uint8_t driver_blake3[BLAKE3_KEY_LEN];
unsigned header_size = get_program_binary_header_size();
st_get_program_binary_driver_sha1(ctx, driver_sha1);
st_get_program_binary_driver_blake3(ctx, driver_blake3);
blob_init(&blob);
@ -251,7 +251,7 @@ _mesa_get_program_binary(struct gl_context *ctx,
blob.out_of_memory)
goto fail;
bool written = write_program_binary(blob.data, blob.size, driver_sha1,
bool written = write_program_binary(blob.data, blob.size, driver_blake3,
binary, buf_size, binary_format);
if (!written || blob.out_of_memory)
goto fail;
@ -273,12 +273,12 @@ _mesa_program_binary(struct gl_context *ctx, struct gl_shader_program *sh_prog,
GLenum binary_format, const GLvoid *binary,
GLsizei length)
{
uint8_t driver_sha1[BLAKE3_KEY_LEN];
uint8_t driver_blake3[BLAKE3_KEY_LEN];
unsigned header_size = get_program_binary_header_size();
st_get_program_binary_driver_sha1(ctx, driver_sha1);
st_get_program_binary_driver_blake3(ctx, driver_blake3);
const void *payload = get_program_binary_payload(binary_format, driver_sha1,
const void *payload = get_program_binary_payload(binary_format, driver_blake3,
binary, length);
if (payload == NULL) {

2
src/mesa/main/shader_types.h
View file

@ -180,7 +180,7 @@ struct gl_shader
enum gl_compile_status CompileStatus;
/** BLAKE3 of the pre-processed source used by the disk cache. */
uint8_t disk_cache_sha1[BLAKE3_KEY_LEN];
uint8_t disk_cache_blake3[BLAKE3_KEY_LEN];
/** BLAKE3 of the original source before replacement, set by glShaderSource. */
blake3_hash source_blake3;
/** BLAKE3 of FallbackSource (a copy of some original source before replacement). */

2
src/mesa/state_tracker/st_extensions.c
View file

@ -1223,7 +1223,7 @@ void st_init_extensions(struct pipe_screen *screen,
consts->AllowGLSLBuiltinVariableRedeclaration = options->allow_glsl_builtin_variable_redeclaration;
consts->dri_config_options_sha1 = options->config_options_sha1;
consts->dri_config_options_blake3 = options->config_options_blake3;
consts->AllowGLSLCrossStageInterpolationMismatch = options->allow_glsl_cross_stage_interpolation_mismatch;

2
src/mesa/state_tracker/st_shader_cache.c
View file

@ -34,7 +34,7 @@
#include "util/perf/cpu_trace.h"
void
st_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *blake3)
st_get_program_binary_driver_blake3(struct gl_context *ctx, uint8_t *blake3)
{
disk_cache_compute_key(ctx->Cache, NULL, 0, blake3);
}

2
src/mesa/state_tracker/st_shader_cache.h
View file

@ -35,7 +35,7 @@ extern "C" {
#endif
void
st_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *blake3);
st_get_program_binary_driver_blake3(struct gl_context *ctx, uint8_t *blake3);
void
st_serialise_nir_program(struct gl_context *ctx, struct gl_program *prog);

4
src/vulkan/runtime/vk_pipeline.c
View file

@ -308,12 +308,12 @@ void
vk_pipeline_hash_shader_stage(VkPipelineCreateFlags2KHR pipeline_flags,
const VkPipelineShaderStageCreateInfo *info,
const struct vk_pipeline_robustness_state *rstate,
unsigned char *stage_sha1)
unsigned char *stage_blake3)
{
blake3_hash blake_hash;
vk_pipeline_hash_shader_stage_blake3(pipeline_flags, info, rstate, blake_hash);
_mesa_blake3_compute(blake_hash, sizeof(blake_hash), stage_sha1);
_mesa_blake3_compute(blake_hash, sizeof(blake_hash), stage_blake3);
}
static VkPipelineRobustnessBufferBehaviorEXT

2
src/vulkan/runtime/vk_pipeline.h
View file

@ -95,7 +95,7 @@ void
vk_pipeline_hash_shader_stage(VkPipelineCreateFlags2KHR pipeline_flags,
const VkPipelineShaderStageCreateInfo *info,
const struct vk_pipeline_robustness_state *rstate,
unsigned char *stage_sha1);
unsigned char *stage_blake3);
void
vk_pipeline_robustness_state_fill(const struct vk_device *device,