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ethosu: Fix scalar ADD on U85
They added new registers tot he command stream, with a new bitfield layout. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39611>
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parent
818e1835d7
commit
2a6d181bc6
2 changed files with 40 additions and 7 deletions
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@ -539,16 +539,42 @@ emit_pooling(struct ethosu_subgraph *subgraph, struct ethosu_operation *operatio
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emit_acc_format(subgraph, operation);
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}
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static void
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emit_ifm2_precision(struct ethosu_subgraph *subgraph,
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struct ethosu_operation *operation,
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bool has_scalar)
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{
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struct ethosu_tensor *tensor = ethosu_find_tensor(subgraph, operation->ifm2.tensor_idx);
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unsigned prec = 0;
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prec |= NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE(operation->ifm2.is_signed);
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prec |= NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION(operation->ifm2.precision);
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if (tensor->layout == ETHOSU_LAYOUT_NHCWB16)
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prec |= NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT(1);
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/* Vela: scalar → NONE(3), non-scalar → TILE2X2(0) */
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if (has_scalar)
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prec |= NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE(3);
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EMIT0(NPU_SET_IFM2_PRECISION, prec);
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}
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static void
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emit_ifm2(struct ethosu_subgraph *subgraph, struct ethosu_operation *operation, bool has_scalar)
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{
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if (!has_scalar) {
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if (has_scalar) {
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if (ethosu_is_u65(ethosu_screen(subgraph->base.context->screen)))
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EMIT0(NPU_SET_IFM2_SCALAR, operation->ifm2.scalar);
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else {
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emit_ifm2_precision(subgraph, operation, true);
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EMIT1(NPU_SET_OP_SCALAR, 0, operation->ifm2.scalar);
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}
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} else {
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EMIT0(NPU_SET_IFM2_REGION, IO_REGION);
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emit_addresses(subgraph, &operation->ifm2, NPU_SET_IFM2_BASE0, NPU_SET_IFM2_BASE1, NPU_SET_IFM2_BASE2, NPU_SET_IFM2_BASE3);
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emit_tiles(subgraph, &operation->ifm2, NPU_SET_IFM2_HEIGHT0_M1, NPU_SET_IFM2_HEIGHT1_M1, NPU_SET_IFM2_WIDTH0_M1);
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emit_strides(subgraph, &operation->ifm2, NPU_SET_IFM2_STRIDE_C, NPU_SET_IFM2_STRIDE_Y, NPU_SET_IFM2_STRIDE_X);
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} else {
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EMIT0(NPU_SET_IFM2_SCALAR, operation->ifm2.scalar);
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}
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EMIT0(NPU_SET_IFM2_ZERO_POINT, operation->ifm2.zero_point);
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}
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@ -242,10 +242,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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<bitfield name="param" low="0" high="15" type="uint"/>
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</reg32>
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<reg32 offset="0x185" name="NPU_SET_IFM2_PRECISION">
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<bitfield name="reserved1" low="8" high="15" type="uint"/>
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<bitfield name="format" low="6" high="7" type="uint"/>
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<bitfield name="reserved0" low="4" high="5" type="uint"/>
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<bitfield name="precision" low="0" high="3" type="uint"/>
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<bitfield name="activation_storage" low="14" high="15" type="uint"/>
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<bitfield name="reserved3" low="8" high="13" type="uint"/>
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<bitfield name="activation_format" low="6" high="7" type="uint"/>
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<bitfield name="reserved2" low="4" high="5" type="uint"/>
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<bitfield name="activation_precision" low="2" high="3" type="uint"/>
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<bitfield name="reserved1" low="1" high="1" type="uint"/>
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<bitfield name="activation_type" low="0" high="0" type="uint"/>
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</reg32>
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<reg32 offset="0x189" name="NPU_SET_IFM2_ZERO_POINT">
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<bitfield name="param" low="0" high="15" type="uint"/>
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@ -379,6 +382,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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<bitfield name="param" low="2" high="17" type="uint"/>
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<bitfield name="payload_size" low="0" high="1" type="uint"/>
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</reg32>
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<reg32 offset="0x39" name="NPU_SET_OP_SCALAR">
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<bitfield name="param" low="2" high="17" type="uint"/>
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<bitfield name="payload_size" low="0" high="1" type="uint"/>
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</reg32>
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<reg32 offset="0x80" name="NPU_SET_IFM2_BASE0">
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<bitfield name="reserved0" low="2" high="17" type="uint"/>
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<bitfield name="payload_size" low="0" high="1" type="uint"/>
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