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Inline mesa_sha1, SHA1_CTX

Browse source 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
This commit is contained in:
Marek Olšák 2026-03-12 20:34:57 -04:00 • committed by Marge Bot
parent 0da88d237a
commit a965ada6ee
66 changed files with 120 additions and 125 deletions
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4
src/amd/common/ac_surface_modifier_test.c
View file

@ -117,7 +117,7 @@ static void gfx9_generate_hash(struct ac_addrlib *ac_addrlib,
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
srandom(53);
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size));
@ -207,7 +207,7 @@ static void gfx12_generate_hash(struct ac_addrlib *ac_addrlib,
ADDR_HANDLE addrlib = ac_addrlib_get_handle(ac_addrlib);
srandom(53);
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size));

2
src/amd/vulkan/layers/radv_sqtt_layer.c
View file

@ -1594,7 +1594,7 @@ radv_add_rt_record(struct radv_device *device, struct rgp_code_object *code_obje
static void
compute_unique_rt_sha(uint64_t pipeline_hash, unsigned index, unsigned char sha1[BLAKE3_KEY_LEN])
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &pipeline_hash, sizeof(pipeline_hash));
_mesa_sha1_update(&ctx, &index, sizeof(index));

2
src/amd/vulkan/radv_physical_device.c
View file

@ -316,7 +316,7 @@ radv_physical_device_init_cache_key(struct radv_physical_device *pdev)
static int
radv_device_get_cache_uuid(struct radv_physical_device *pdev, void *uuid)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
memset(uuid, 0, VK_UUID_SIZE);

4
src/amd/vulkan/radv_pipeline.c
View file

@ -1137,7 +1137,7 @@ radv_copy_shader_stage_create_info(struct radv_device *device, uint32_t stageCou
void
radv_pipeline_hash(const struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
struct mesa_sha1 *ctx)
blake3_hasher *ctx)
{
_mesa_sha1_update(ctx, device->cache_hash, sizeof(device->cache_hash));
if (pipeline_layout)
@ -1146,7 +1146,7 @@ radv_pipeline_hash(const struct radv_device *device, const struct radv_pipeline_
void
radv_pipeline_hash_shader_stage(VkPipelineCreateFlags2 pipeline_flags, const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_shader_stage_key *stage_key, struct mesa_sha1 *ctx)
const struct radv_shader_stage_key *stage_key, blake3_hasher *ctx)
{
unsigned char shader_sha1[BLAKE3_KEY_LEN];

4
src/amd/vulkan/radv_pipeline.h
View file

@ -104,11 +104,11 @@ VkPipelineShaderStageCreateInfo *radv_copy_shader_stage_create_info(struct radv_
void *mem_ctx);
void radv_pipeline_hash(const struct radv_device *device, const struct radv_pipeline_layout *pipeline_layout,
struct mesa_sha1 *ctx);
blake3_hasher *ctx);
void radv_pipeline_hash_shader_stage(VkPipelineCreateFlags2 pipeline_flags,
const VkPipelineShaderStageCreateInfo *sinfo,
const struct radv_shader_stage_key *stage_key, struct mesa_sha1 *ctx);
const struct radv_shader_stage_key *stage_key, blake3_hasher *ctx);
void radv_pipeline_report_pso_history(const struct radv_device *device, struct radv_pipeline *pipeline);

2
src/amd/vulkan/radv_pipeline_compute.c
View file

@ -161,7 +161,7 @@ radv_compute_pipeline_hash(const struct radv_device *device, const VkComputePipe
VkPipelineCreateFlags2 create_flags = vk_compute_pipeline_create_flags(pCreateInfo);
VK_FROM_HANDLE(radv_pipeline_layout, pipeline_layout, pCreateInfo->layout);
const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->stage;
struct mesa_sha1 ctx;
blake3_hasher ctx;
struct radv_shader_stage_key stage_key =
radv_pipeline_get_shader_key(device, sinfo, create_flags, pCreateInfo->pNext);

2
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -3085,7 +3085,7 @@ void
radv_graphics_pipeline_hash(const struct radv_device *device, const struct radv_graphics_pipeline_state *gfx_state,
unsigned char *hash)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
radv_pipeline_hash(device, &gfx_state->layout, &ctx);

6
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -124,7 +124,7 @@ radv_create_group_handles(struct radv_device *device, const VkRayTracingPipeline
if (group_info->intersectionShader != VK_SHADER_UNUSED_KHR) {
unsigned char sha1[BLAKE3_KEY_LEN];
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, stages[group_info->intersectionShader].sha1, BLAKE3_KEY_LEN);
@ -318,7 +318,7 @@ radv_init_rt_stage_hashes(const struct radv_device *device, VkPipelineCreateFlag
for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) {
const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[idx];
mesa_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage);
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
radv_pipeline_hash_shader_stage(pipeline_flags, sinfo, &stage_keys[s], &ctx);
@ -1076,7 +1076,7 @@ radv_ray_tracing_pipeline_hash(const struct radv_device *device, const VkRayTrac
const struct radv_ray_tracing_state_key *rt_state, unsigned char *hash)
{
VK_FROM_HANDLE(radv_pipeline_layout, layout, pCreateInfo->layout);
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
radv_pipeline_hash(device, layout, &ctx);

4
src/asahi/lib/agx_device.c
View file

@ -887,7 +887,7 @@ agx_get_gpu_timestamp(struct agx_device *dev)
void
agx_get_device_uuid(const struct agx_device *dev, void *uuid)
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
/* The device UUID uniquely identifies the given device within the machine.
@ -922,7 +922,7 @@ agx_get_driver_uuid(void *uuid)
* driver. People who want to share memory need to also check the device
* UUID.
*/
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));

4
src/asahi/vulkan/hk_physical_device.c
View file

@ -1089,7 +1089,7 @@ hk_get_device_properties(const struct agx_device *dev,
properties->identicalMemoryTypeRequirements = true;
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);
@ -1107,7 +1107,7 @@ hk_physical_device_init_pipeline_cache(struct hk_physical_device *pdev)
{
struct hk_instance *instance = hk_physical_device_instance(pdev);
struct mesa_sha1 sha_ctx;
blake3_hasher sha_ctx;
_mesa_sha1_init(&sha_ctx);
_mesa_sha1_update(&sha_ctx, instance->driver_build_sha,

8
src/broadcom/vulkan/v3dv_descriptor_set.c
View file

@ -279,7 +279,7 @@ v3dv_descriptor_map_get_texture_shader_state(struct v3dv_device *device,
#define SHA1_UPDATE_VALUE(ctx, x) _mesa_sha1_update(ctx, &(x), sizeof(x));
static void
sha1_update_ycbcr_conversion(struct mesa_sha1 *ctx,
sha1_update_ycbcr_conversion(blake3_hasher *ctx,
const struct vk_ycbcr_conversion_state *conversion)
{
SHA1_UPDATE_VALUE(ctx, conversion->format);
@ -291,7 +291,7 @@ sha1_update_ycbcr_conversion(struct mesa_sha1 *ctx,
}
static void
sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_binding_layout(blake3_hasher *ctx,
const struct v3dv_descriptor_set_binding_layout *layout,
const struct v3dv_descriptor_set_layout *set_layout)
{
@ -317,7 +317,7 @@ sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
}
static void
sha1_update_descriptor_set_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_layout(blake3_hasher *ctx,
const struct v3dv_descriptor_set_layout *layout)
{
SHA1_UPDATE_VALUE(ctx, layout->flags);
@ -384,7 +384,7 @@ v3dv_CreatePipelineLayout(VkDevice _device,
layout->dynamic_offset_count = dynamic_offset_count;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
for (unsigned s = 0; s < layout->num_sets; s++) {
sha1_update_descriptor_set_layout(&ctx, layout->set[s].layout);

2
src/broadcom/vulkan/v3dv_device.c
View file

@ -817,7 +817,7 @@ init_uuids(struct v3dv_physical_device *device)
uint32_t vendor_id = v3dv_physical_device_vendor_id(device);
uint32_t device_id = v3dv_physical_device_device_id(device);
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
STATIC_ASSERT(VK_UUID_SIZE <= sizeof(sha1));

4
src/broadcom/vulkan/v3dv_pipeline.c
View file

@ -1517,7 +1517,7 @@ pipeline_hash_graphics(const struct v3dv_pipeline *pipeline,
struct v3dv_pipeline_key *key,
unsigned char *sha1_out)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
if (pipeline->layout) {
@ -1552,7 +1552,7 @@ pipeline_hash_compute(const struct v3dv_pipeline *pipeline,
struct v3dv_pipeline_key *key,
unsigned char *sha1_out)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
if (pipeline->layout) {

2
src/compiler/clc/nir_load_libclc.c
View file

@ -122,7 +122,7 @@ open_clc_data(struct clc_data *clc, unsigned ptr_bit_size)
return false;
}
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, clc->file->sys_path, strlen(clc->file->sys_path));
#if defined(__APPLE__) || defined(__MACOSX)

4
src/freedreno/common/freedreno_uuid.c
View file

@ -27,7 +27,7 @@ fd_get_driver_uuid(void *uuid)
* driver. People who want to share memory need to also check the device
* UUID.
*/
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));
@ -42,7 +42,7 @@ fd_get_driver_uuid(void *uuid)
void
fd_get_device_uuid(void *uuid, const struct fd_dev_id *id)
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
/* The device UUID uniquely identifies the given device within the machine.

4
src/freedreno/ir3/ir3_disk_cache.c
View file

@ -42,7 +42,7 @@ ir3_disk_cache_init(struct ir3_compiler *compiler)
const uint8_t *id_sha1 = build_id_data(note);
assert(id_sha1);
struct mesa_sha1 ctx;
blake3_hasher ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, id_sha1, build_id_len);
@ -64,7 +64,7 @@ ir3_disk_cache_init_shader_key(struct ir3_compiler *compiler,
if (!compiler->disk_cache && !ir3_shader_bisect_need_shader_key())
return;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);

2
src/freedreno/ir3/ir3_shader.c
View file

@ -399,7 +399,7 @@ assemble_variant(struct ir3_shader_variant *v, bool internal)
unsigned char sha1[BLAKE3_KEY_LEN + 1];
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, v->bin, v->info.size);

8
src/freedreno/vulkan/tu_descriptor_set.cc
View file

@ -454,7 +454,7 @@ tu_GetDescriptorSetLayoutBindingOffsetEXT(
#define SHA1_UPDATE_VALUE(ctx, x) _mesa_sha1_update(ctx, &(x), sizeof(x));
static void
sha1_update_ycbcr_sampler(struct mesa_sha1 *ctx,
sha1_update_ycbcr_sampler(blake3_hasher *ctx,
const struct vk_ycbcr_conversion_state *sampler)
{
SHA1_UPDATE_VALUE(ctx, sampler->ycbcr_model);
@ -463,7 +463,7 @@ sha1_update_ycbcr_sampler(struct mesa_sha1 *ctx,
}
static void
sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_binding_layout(blake3_hasher *ctx,
const struct tu_descriptor_set_binding_layout *layout,
const struct tu_descriptor_set_layout *set_layout)
{
@ -498,7 +498,7 @@ sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
static void
sha1_update_descriptor_set_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_layout(blake3_hasher *ctx,
const struct tu_descriptor_set_layout *layout)
{
SHA1_UPDATE_VALUE(ctx, layout->has_variable_descriptors);
@ -516,7 +516,7 @@ sha1_update_descriptor_set_layout(struct mesa_sha1 *ctx,
void
tu_pipeline_layout_init(struct tu_pipeline_layout *layout)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
for (unsigned s = 0; s < layout->num_sets; s++) {
if (layout->set[s].layout)

4
src/freedreno/vulkan/tu_device.cc
View file

@ -55,7 +55,7 @@ uint64_t os_page_size = 4096;
static int
tu_device_get_cache_uuid(struct tu_physical_device *device, void *uuid)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
/* Note: IR3_SHADER_DEBUG also affects compilation, but it's not
* initialized until after compiler creation so we have to add it to the
@ -1496,7 +1496,7 @@ tu_get_properties(struct tu_physical_device *pdevice,
props->identicalMemoryTypeRequirements = true;
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);

6
src/freedreno/vulkan/tu_pipeline.cc
View file

@ -1525,7 +1525,7 @@ tu_append_executable(struct tu_pipeline *pipeline,
}
static void
tu_hash_stage(struct mesa_sha1 *ctx,
tu_hash_stage(blake3_hasher *ctx,
VkPipelineCreateFlags2KHR pipeline_flags,
const VkPipelineShaderStageCreateInfo *stage,
const nir_shader *nir,
@ -1555,7 +1555,7 @@ tu_hash_shaders(unsigned char *hash,
const struct tu_shader_key *keys,
VkGraphicsPipelineLibraryFlagsEXT state)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
@ -1580,7 +1580,7 @@ tu_hash_compute(unsigned char *hash,
const struct tu_pipeline_layout *layout,
const struct tu_shader_key *key)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);

2
src/gallium/auxiliary/draw/draw_llvm.c
View file

@ -453,7 +453,7 @@ draw_get_ir_cache_key(struct nir_shader *nir,
ir_binary = blob.data;
ir_size = blob.size;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, key, key_size);
_mesa_sha1_update(&ctx, ir_binary, ir_size);

2
src/gallium/auxiliary/util/u_live_shader_cache.c
View file

@ -98,7 +98,7 @@ util_live_shader_cache_get(struct pipe_context *ctx,
}
/* Compute SHA1 of pipe_shader_state. */
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, ir_binary, ir_size);

2
src/gallium/drivers/d3d12/d3d12_screen.cpp
View file

@ -1734,7 +1734,7 @@ d3d12_init_screen(struct d3d12_screen *screen, IUnknown *adapter)
#endif
const char *mesa_version = "Mesa " PACKAGE_VERSION MESA_GIT_SHA1;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
STATIC_ASSERT(PIPE_UUID_SIZE <= sizeof(sha1));

2
src/gallium/drivers/etnaviv/etnaviv_disk_cache.c
View file

@ -56,7 +56,7 @@ etna_disk_cache_init_shader_key(struct etna_compiler *compiler, struct etna_shad
if (!compiler->disk_cache)
return;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);

2
src/gallium/drivers/iris/iris_program.c
View file

@ -1817,7 +1817,7 @@ iris_debug_archiver_open(void *tmp_ctx, struct iris_screen *screen,
char name[BLAKE3_HEX_LEN + 5] = {};
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char hash[BLAKE3_KEY_LEN];
_mesa_sha1_init(&ctx);

4
src/gallium/drivers/llvmpipe/lp_screen.c
View file

@ -869,7 +869,7 @@ llvmpipe_fence_finish(struct pipe_screen *screen,
static void
update_cache_sha1_cpu(struct mesa_sha1 *ctx)
update_cache_sha1_cpu(blake3_hasher *ctx)
{
const struct util_cpu_caps_t *cpu_caps = util_get_cpu_caps();
/*
@ -885,7 +885,7 @@ update_cache_sha1_cpu(struct mesa_sha1 *ctx)
static void
lp_disk_cache_create(struct llvmpipe_screen *screen)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned gallivm_perf = gallivm_get_perf_flags();
unsigned char sha1[BLAKE3_KEY_LEN];
char cache_id[BLAKE3_HEX_LEN];

2
src/gallium/drivers/llvmpipe/lp_state_cs.c
View file

@ -1262,7 +1262,7 @@ lp_cs_get_ir_cache_key(struct lp_compute_shader_variant *variant,
ir_binary = blob.data;
ir_size = blob.size;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &variant->key, variant->shader->variant_key_size);
_mesa_sha1_update(&ctx, ir_binary, ir_size);

2
src/gallium/drivers/llvmpipe/lp_state_fs.c
View file

@ -3804,7 +3804,7 @@ lp_fs_get_ir_cache_key(struct lp_fragment_shader_variant *variant,
ir_binary = blob.data;
ir_size = blob.size;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &variant->key, variant->shader->variant_key_size);
_mesa_sha1_update(&ctx, ir_binary, ir_size);

12
src/gallium/drivers/llvmpipe/lp_texture_handle.c
View file

@ -374,7 +374,7 @@ compile_image_function(struct llvmpipe_context *ctx, struct lp_static_texture_st
return NULL;
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, image_function_base_hash, strlen(image_function_base_hash));
_mesa_sha1_update(&hash_ctx, &local_texture, sizeof(local_texture));
@ -531,7 +531,7 @@ compile_sample_function(struct llvmpipe_context *ctx, struct lp_texture_handle_s
}
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, sample_function_base_hash, strlen(sample_function_base_hash));
_mesa_sha1_update(&hash_ctx, texture, sizeof(*texture));
@ -642,7 +642,7 @@ static void *
compile_size_function(struct llvmpipe_context *ctx, struct lp_texture_handle_state *texture, bool samples)
{
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, size_function_base_hash, strlen(size_function_base_hash));
_mesa_sha1_update(&hash_ctx, texture, sizeof(*texture));
@ -869,7 +869,7 @@ static void *
compile_jit_sample_function(struct llvmpipe_context *ctx, uint32_t sample_key)
{
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, jit_sample_function_base_hash, strlen(jit_sample_function_base_hash));
_mesa_sha1_update(&hash_ctx, &sample_key, sizeof(sample_key));
@ -990,7 +990,7 @@ static void *
compile_jit_fetch_function(struct llvmpipe_context *ctx, uint32_t sample_key)
{
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, jit_fetch_function_base_hash, strlen(jit_fetch_function_base_hash));
_mesa_sha1_update(&hash_ctx, &sample_key, sizeof(sample_key));
@ -1109,7 +1109,7 @@ static void *
compile_jit_size_function(struct llvmpipe_context *ctx, bool samples)
{
uint8_t cache_key[BLAKE3_KEY_LEN];
struct mesa_sha1 hash_ctx;
blake3_hasher hash_ctx;
_mesa_sha1_init(&hash_ctx);
_mesa_sha1_update(&hash_ctx, jit_size_function_base_hash, strlen(jit_size_function_base_hash));
_mesa_sha1_update(&hash_ctx, &samples, sizeof(samples));

4
src/gallium/drivers/nouveau/nouveau_screen.c
View file

@ -175,7 +175,7 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
static void
nouveau_disk_cache_create(struct nouveau_screen *screen)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
char cache_id[BLAKE3_HEX_LEN];
uint64_t driver_flags = 0;
@ -275,7 +275,7 @@ static void
nouveau_driver_uuid(struct pipe_screen *screen, char *uuid)
{
const char* driver = PACKAGE_VERSION MESA_GIT_SHA1;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);

2
src/gallium/drivers/r300/r300_screen.c
View file

@ -79,7 +79,7 @@ static const char* r300_get_name(struct pipe_screen* pscreen)
static void r300_disk_cache_create(struct r300_screen* r300screen)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
char cache_id[BLAKE3_HEX_LEN];

4
src/gallium/drivers/r600/r600_pipe_common.c
View file

@ -753,7 +753,7 @@ static void r600_disk_cache_create(struct r600_common_screen *rscreen)
if (rscreen->debug_flags & DBG_ALL_SHADERS)
return;
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
char cache_id[BLAKE3_HEX_LEN];
@ -934,7 +934,7 @@ static void r600_get_driver_uuid(UNUSED struct pipe_screen *screen, char *uuid)
* OpenGL driver. People who want to share memory need to also check
* the device UUID.
*/
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -1181,7 +1181,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
if (sscreen->shader_debug_flags & DBG_ALL_SHADERS)
return;
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
char cache_id[BLAKE3_HEX_LEN];

2
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -184,7 +184,7 @@ void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
if (sel->screen->options.clear_lds)
shader_variant_flags |= 1 << 12;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &shader_variant_flags, 4);
_mesa_sha1_update(&ctx, ir_binary, ir_size);

2
src/gallium/drivers/v3d/v3d_program.c
View file

@ -974,7 +974,7 @@ cache_hash(const void *_key, uint32_t key_size)
{
const struct v3d_cache_key *key = (struct v3d_cache_key *) _key;
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, key->key, key_size);

2
src/gallium/drivers/virgl/virgl_screen.c
View file

@ -901,7 +901,7 @@ static struct disk_cache *virgl_get_disk_shader_cache (struct pipe_screen *pscre
static void virgl_disk_cache_create(struct virgl_screen *screen)
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
#if HAVE_BUILD_ID

4
src/gallium/frontends/lavapipe/lvp_pipeline.c
View file

@ -1282,7 +1282,7 @@ create_shader_object(struct lvp_device *device, const VkShaderCreateInfoEXT *pCr
size_t size = pCreateInfo->codeSize - BLAKE3_KEY_LEN - VK_UUID_SIZE;
unsigned char sha1[BLAKE3_KEY_LEN];
struct mesa_sha1 sctx;
blake3_hasher sctx;
_mesa_sha1_init(&sctx);
_mesa_sha1_update(&sctx, data + BLAKE3_KEY_LEN + VK_UUID_SIZE, size);
_mesa_sha1_final(&sctx, sha1);
@ -1381,7 +1381,7 @@ VKAPI_ATTR VkResult VKAPI_CALL lvp_GetShaderBinaryDataEXT(
*pDataSize = MIN2(*pDataSize, shader->blob.size + BLAKE3_KEY_LEN + VK_UUID_SIZE);
uint8_t *data = pData;
lvp_device_get_cache_uuid(data);
struct mesa_sha1 sctx;
blake3_hasher sctx;
_mesa_sha1_init(&sctx);
_mesa_sha1_update(&sctx, shader->blob.data, shader->blob.size);
_mesa_sha1_final(&sctx, data + VK_UUID_SIZE);

2
src/gallium/frontends/rusticl/mesa/util/disk_cache.rs
View file

@ -79,7 +79,7 @@ impl DiskCacheBorrowed {
impl DiskCache {
pub fn new(name: &CStr, func_ptrs: &[*mut c_void], flags: u64) -> Option<Self> {
let mut sha_ctx = SHA1_CTX::default();
let mut sha_ctx = blake3_hasher::default();
let mut sha = [0; BLAKE3_KEY_LEN as usize];
let mut cache_id = [0; BLAKE3_HEX_LEN as usize];

4
src/imagination/vulkan/pvr_physical_device.c
View file

@ -881,7 +881,7 @@ pvr_get_device_uuid(const struct pvr_device_info *dev_info,
{
uint64_t bvnc = pvr_get_packed_bvnc(dev_info);
static const char *device_str = "pvr";
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, device_str, strlen(device_str));
@ -895,7 +895,7 @@ pvr_get_cache_uuid(const struct pvr_physical_device *const pdevice,
{
const struct pvr_instance *instance = pdevice->instance;
static const char *cache_str = "cache";
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, cache_str, strlen(cache_str));

2
src/intel/common/intel_uuid.c
View file

@ -75,7 +75,7 @@ intel_uuid_compute_driver_id(uint8_t *uuid,
size_t size)
{
const char* intelDriver = PACKAGE_VERSION MESA_GIT_SHA1;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
assert(size <= sizeof(sha1));

2
src/intel/compiler/brw/brw_compiler.c
View file

@ -282,7 +282,7 @@ brw_get_compiler_config_value(const struct brw_compiler *compiler)
void
brw_device_sha1(char *hex,
const struct intel_device_info *devinfo) {
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
brw_device_sha1_update(&ctx, devinfo);
unsigned char result[BLAKE3_KEY_LEN];

2
src/intel/compiler/brw/brw_compiler.h
View file

@ -1301,7 +1301,7 @@ brw_device_sha1(char *hex, const struct intel_device_info *devinfo);
* sha1_ctx.
*/
void
brw_device_sha1_update(struct mesa_sha1 *sha1_ctx,
brw_device_sha1_update(blake3_hasher *sha1_ctx,
const struct intel_device_info *devinfo);
unsigned

2
src/intel/compiler/brw_device_sha1_gen_c.py
View file

@ -25,7 +25,7 @@ template = COPYRIGHT + """
#define SHA_UPDATE_FIELD(field) _mesa_sha1_update(ctx, &devinfo->field, sizeof(devinfo->field))
void
brw_device_sha1_update(struct mesa_sha1 *ctx,
brw_device_sha1_update(blake3_hasher *ctx,
const struct intel_device_info *devinfo) {
% for member in compiler_fields:
% if member.ray_tracing_field:

2
src/intel/perf/intel_perf.c
View file

@ -797,7 +797,7 @@ intel_perf_store_configuration(struct intel_perf_config *perf_cfg, int fd,
if (guid)
return kmd_add_config(perf_cfg, fd, config, guid);
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
if (config->flex_regs) {

4
src/intel/vulkan/anv_physical_device.c
View file

@ -1795,7 +1795,7 @@ get_properties(const struct anv_physical_device *pdevice,
* different tilings sometimes (see isl_gfx7.c).
*/
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);
@ -2374,7 +2374,7 @@ anv_physical_device_init_uuids(struct anv_physical_device *device)
copy_build_id_to_sha1(device->driver_build_sha1, note);
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
STATIC_ASSERT(VK_UUID_SIZE <= sizeof(sha1));

2
src/intel/vulkan/anv_pipeline_cache.c
View file

@ -326,7 +326,7 @@ anv_load_fp64_shader(struct anv_device *device)
&device->physical->compiler->nir_options[MESA_SHADER_VERTEX];
const char* shader_name = "float64_spv_lib";
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, shader_name, strlen(shader_name));

6
src/intel/vulkan/anv_shader_compile.c
View file

@ -151,7 +151,7 @@ anv_shader_init_uuid(struct anv_physical_device *device)
* compiler's output, not having that workaroung enabled with an app
* expecting fp64 support will just crash in the backend.
*/
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
const bool indirect_descriptors = device->indirect_descriptors;
@ -1818,7 +1818,7 @@ anv_debug_archiver_init(void *mem_ctx, struct anv_shader_data *shaders_data,
*/
unsigned char linked_hash[BLAKE3_KEY_LEN];
if (shader_count > 1) {
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
for (uint32_t s = 0; s < shader_count; s++) {
@ -1836,7 +1836,7 @@ anv_debug_archiver_init(void *mem_ctx, struct anv_shader_data *shaders_data,
char name[BLAKE3_HEX_LEN + 4] = {};
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
unsigned char hash[BLAKE3_KEY_LEN];
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, info->nir->info.source_blake3, BLAKE3_OUT_LEN);

8
src/intel/vulkan_hasvk/anv_descriptor_set.c
View file

@ -701,7 +701,7 @@ void anv_DestroyDescriptorSetLayout(
#define SHA1_UPDATE_VALUE(ctx, x) _mesa_sha1_update(ctx, &(x), sizeof(x));
static void
sha1_update_immutable_sampler(struct mesa_sha1 *ctx,
sha1_update_immutable_sampler(blake3_hasher *ctx,
const struct anv_sampler *sampler)
{
if (!sampler->conversion)
@ -713,7 +713,7 @@ sha1_update_immutable_sampler(struct mesa_sha1 *ctx,
}
static void
sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_binding_layout(blake3_hasher *ctx,
const struct anv_descriptor_set_binding_layout *layout)
{
SHA1_UPDATE_VALUE(ctx, layout->flags);
@ -732,7 +732,7 @@ sha1_update_descriptor_set_binding_layout(struct mesa_sha1 *ctx,
}
static void
sha1_update_descriptor_set_layout(struct mesa_sha1 *ctx,
sha1_update_descriptor_set_layout(blake3_hasher *ctx,
const struct anv_descriptor_set_layout *layout)
{
SHA1_UPDATE_VALUE(ctx, layout->binding_count);
@ -782,7 +782,7 @@ VkResult anv_CreatePipelineLayout(
}
assert(dynamic_offset_count < MAX_DYNAMIC_BUFFERS);
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
for (unsigned s = 0; s < layout->num_sets; s++) {
sha1_update_descriptor_set_layout(&ctx, layout->set[s].layout);

2
src/intel/vulkan_hasvk/anv_device.c
View file

@ -1423,7 +1423,7 @@ anv_physical_device_init_uuids(struct anv_physical_device *device)
copy_build_id_to_sha1(device->driver_build_sha1, note);
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
STATIC_ASSERT(VK_UUID_SIZE <= sizeof(sha1));

4
src/intel/vulkan_hasvk/anv_pipeline.c
View file

@ -371,7 +371,7 @@ anv_pipeline_hash_graphics(struct anv_graphics_pipeline *pipeline,
struct anv_pipeline_stage *stages,
unsigned char *sha1_out)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, &pipeline->view_mask,
@ -397,7 +397,7 @@ anv_pipeline_hash_compute(struct anv_compute_pipeline *pipeline,
struct anv_pipeline_stage *stage,
unsigned char *sha1_out)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
if (layout)

2
src/kosmickrisp/vulkan/kk_physical_device.c
View file

@ -736,7 +736,7 @@ kk_physical_device_init_pipeline_cache(struct kk_physical_device *pdev)
{
struct kk_instance *instance = kk_physical_device_instance(pdev);
struct mesa_sha1 sha_ctx;
blake3_hasher sha_ctx;
_mesa_sha1_init(&sha_ctx);
_mesa_sha1_update(&sha_ctx, instance->driver_build_sha,

2
src/microsoft/vulkan/dzn_descriptor_set.c
View file

@ -592,7 +592,7 @@ dzn_pipeline_layout_hash_stages(struct dzn_pipeline_layout *layout,
if (!(stages & BITFIELD_BIT(stage)))
continue;
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
for (uint32_t set = 0; set < info->setLayoutCount; set++) {

2
src/microsoft/vulkan/dzn_device.c
View file

@ -351,7 +351,7 @@ dzn_physical_device_init_uuids(struct dzn_physical_device *pdev)
{
const char *mesa_version = "Mesa " PACKAGE_VERSION MESA_GIT_SHA1;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
STATIC_ASSERT(VK_UUID_SIZE <= sizeof(sha1));

16
src/microsoft/vulkan/dzn_pipeline.c
View file

@ -347,7 +347,7 @@ adjust_var_bindings(nir_shader *shader,
uint8_t *bindings_hash)
{
uint32_t modes = nir_var_image | nir_var_uniform | nir_var_mem_ubo | nir_var_mem_ssbo;
struct mesa_sha1 bindings_hash_ctx;
blake3_hasher bindings_hash_ctx;
if (bindings_hash)
_mesa_sha1_init(&bindings_hash_ctx);
@ -738,7 +738,7 @@ dzn_graphics_pipeline_hash_attribs(D3D12_INPUT_ELEMENT_DESC *attribs,
enum pipe_format *vi_conversions,
uint8_t *result)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, attribs, sizeof(*attribs) * MAX_VERTEX_GENERIC_ATTRIBS);
@ -845,7 +845,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
if (cache) {
dzn_graphics_pipeline_hash_attribs(attribs, vi_conversions, attribs_hash);
struct mesa_sha1 pipeline_hash_ctx;
blake3_hasher pipeline_hash_ctx;
_mesa_sha1_init(&pipeline_hash_ctx);
_mesa_sha1_update(&pipeline_hash_ctx, &device->bindless, sizeof(device->bindless));
@ -886,7 +886,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
dxil_get_nir_compiler_options(&nir_opts, dzn_get_shader_model(pdev), supported_bit_sizes, supported_bit_sizes);
nir_opts.lower_base_vertex = true;
u_foreach_bit(stage, active_stage_mask) {
struct mesa_sha1 nir_hash_ctx;
blake3_hasher nir_hash_ctx;
if (cache) {
_mesa_sha1_init(&nir_hash_ctx);
@ -1011,7 +1011,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
cache ? bindings_hash : NULL);
if (cache) {
struct mesa_sha1 dxil_hash_ctx;
blake3_hasher dxil_hash_ctx;
_mesa_sha1_init(&dxil_hash_ctx);
_mesa_sha1_update(&dxil_hash_ctx, stages[stage].nir_hash, sizeof(stages[stage].nir_hash));
@ -2496,7 +2496,7 @@ dzn_compute_pipeline_compile_shader(struct dzn_device *device,
nir_shader *nir = NULL;
if (cache) {
struct mesa_sha1 pipeline_hash_ctx;
blake3_hasher pipeline_hash_ctx;
_mesa_sha1_init(&pipeline_hash_ctx);
vk_pipeline_hash_shader_stage(pipeline->base.flags, &info->stage, NULL, spirv_hash);
@ -2515,7 +2515,7 @@ dzn_compute_pipeline_compile_shader(struct dzn_device *device,
}
if (cache) {
struct mesa_sha1 nir_hash_ctx;
blake3_hasher nir_hash_ctx;
_mesa_sha1_init(&nir_hash_ctx);
_mesa_sha1_update(&nir_hash_ctx, &device->bindless, sizeof(device->bindless));
_mesa_sha1_update(&nir_hash_ctx, spirv_hash, sizeof(spirv_hash));
@ -2540,7 +2540,7 @@ dzn_compute_pipeline_compile_shader(struct dzn_device *device,
NIR_PASS(_, nir, adjust_var_bindings, device, layout, cache ? bindings_hash : NULL);
if (cache) {
struct mesa_sha1 dxil_hash_ctx;
blake3_hasher dxil_hash_ctx;
_mesa_sha1_init(&dxil_hash_ctx);
_mesa_sha1_update(&dxil_hash_ctx, nir_hash, sizeof(nir_hash));

2
src/nouveau/vulkan/nvk_physical_device.c
View file

@ -1323,7 +1323,7 @@ nvk_physical_device_init_pipeline_cache(struct nvk_physical_device *pdev)
{
const struct nvk_instance *instance = nvk_physical_device_instance(pdev);
struct mesa_sha1 sha_ctx;
blake3_hasher sha_ctx;
_mesa_sha1_init(&sha_ctx);
_mesa_sha1_update(&sha_ctx, instance->driver_build_sha,

2
src/panfrost/vulkan/panvk_physical_device.c
View file

@ -144,7 +144,7 @@ static void
init_shader_caches(struct panvk_physical_device *device,
const struct panvk_instance *instance)
{
struct mesa_sha1 sha_ctx;
blake3_hasher sha_ctx;
_mesa_sha1_init(&sha_ctx);
_mesa_sha1_update(&sha_ctx, instance->driver_build_sha,

2
src/util/disk_cache.c
View file

@ -684,7 +684,7 @@ void
disk_cache_compute_key(struct disk_cache *cache, const void *data, size_t size,
cache_key key)
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, cache->driver_keys_blob,

6
src/util/disk_cache.h
View file

@ -104,7 +104,7 @@ disk_cache_get_function_timestamp(void *ptr, uint32_t* timestamp)
}
static inline bool
disk_cache_get_function_identifier(void *ptr, struct mesa_sha1 *ctx)
disk_cache_get_function_identifier(void *ptr, blake3_hasher *ctx)
{
uint32_t timestamp;
@ -122,10 +122,10 @@ disk_cache_get_function_identifier(void *ptr, struct mesa_sha1 *ctx)
}
#elif DETECT_OS_WINDOWS
bool
disk_cache_get_function_identifier(void *ptr, struct mesa_sha1 *ctx);
disk_cache_get_function_identifier(void *ptr, blake3_hasher *ctx);
#else
static inline bool
disk_cache_get_function_identifier(void *ptr, struct mesa_sha1 *ctx)
disk_cache_get_function_identifier(void *ptr, blake3_hasher *ctx)
{
return false;
}

2
src/util/disk_cache_os.c
View file

@ -43,7 +43,7 @@
#include <windows.h>
bool
disk_cache_get_function_identifier(void *ptr, struct mesa_sha1 *ctx)
disk_cache_get_function_identifier(void *ptr, blake3_hasher *ctx)
{
HMODULE mod = NULL;
GetModuleHandleExW(GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS | GET_MODULE_HANDLE_EX_FLAG_UNCHANGED_REFCOUNT,

2
src/util/mesa-sha1.c
View file

@ -33,7 +33,7 @@
void
_mesa_sha1_compute(const void *data, size_t size, unsigned char result[BLAKE3_KEY_LEN])
{
struct mesa_sha1 ctx;
blake3_hasher ctx;
_mesa_sha1_init(&ctx);
_mesa_sha1_update(&ctx, data, size);

7
src/util/mesa-sha1.h
View file

@ -32,24 +32,23 @@
extern "C" {
#endif
#define mesa_sha1 _SHA1_CTX
#define BLAKE3_KEY_LEN32 (BLAKE3_KEY_LEN / 4)
static inline void
_mesa_sha1_init(struct mesa_sha1 *ctx)
_mesa_sha1_init(blake3_hasher *ctx)
{
SHA1Init(ctx);
}
static inline void
_mesa_sha1_update(struct mesa_sha1 *ctx, const void *data, size_t size)
_mesa_sha1_update(blake3_hasher *ctx, const void *data, size_t size)
{
if (size)
SHA1Update(ctx, (const unsigned char *)data, size);
}
static inline void
_mesa_sha1_final(struct mesa_sha1 *ctx, unsigned char result[BLAKE3_KEY_LEN])
_mesa_sha1_final(blake3_hasher *ctx, unsigned char result[BLAKE3_KEY_LEN])
{
SHA1Final(result, ctx);
}

2
src/util/os_memory_fd.c
View file

@ -58,7 +58,7 @@ struct memory_header {
static void
get_driver_id_sha1_hash(uint8_t sha1[BLAKE3_KEY_LEN], const char *driver_id) {
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
_mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));

16
src/util/sha1/sha1.h
View file

@ -18,26 +18,22 @@
extern "C" {
#endif
typedef struct _SHA1_CTX {
blake3_hasher hasher;
} SHA1_CTX;
static inline void
SHA1Init(SHA1_CTX *context)
SHA1Init(blake3_hasher *context)
{
_mesa_blake3_init(&context->hasher);
_mesa_blake3_init(context);
}
static inline void
SHA1Update(SHA1_CTX *context, const uint8_t *data, size_t len)
SHA1Update(blake3_hasher *context, const uint8_t *data, size_t len)
{
_mesa_blake3_update(&context->hasher, data, len);
_mesa_blake3_update(context, data, len);
}
static inline void
SHA1Final(uint8_t digest[BLAKE3_KEY_LEN], SHA1_CTX *context)
SHA1Final(uint8_t digest[BLAKE3_KEY_LEN], blake3_hasher *context)
{
_mesa_blake3_final(&context->hasher, digest);
_mesa_blake3_final(context, digest);
}
#ifdef __cplusplus

2
src/virtio/vulkan/vn_image.c
View file

@ -92,7 +92,7 @@ vn_image_get_image_reqs_key(struct vn_device *dev,
const VkImageCreateInfo *create_info,
uint8_t *key)
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
if (!dev->image_reqs_cache.ht)
return false;

4
src/virtio/vulkan/vn_physical_device.c
View file

@ -472,7 +472,7 @@ static void
vn_physical_device_init_uuids(struct vn_physical_device *physical_dev)
{
struct vk_properties *props = &physical_dev->base.vk.properties;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
uint8_t sha1[BLAKE3_KEY_LEN];
static_assert(VK_UUID_SIZE <= BLAKE3_KEY_LEN, "");
@ -2370,7 +2370,7 @@ vn_image_get_image_format_key(
const VkImageFormatProperties2 *format_props,
uint8_t *key)
{
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
if (!physical_dev->image_format_cache.ht)
return false;

4
src/vulkan/runtime/vk_shader.c
View file

@ -354,7 +354,7 @@ vk_shader_serialize(struct vk_device *device,
if (blob->data != NULL) {
assert(sizeof(header) <= blob->size);
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
/* Hash the header with a zero SHA1 */
@ -427,7 +427,7 @@ vk_shader_deserialize(struct vk_device *device,
assert(blob.current == (uint8_t *)data + sizeof(header));
blob.end = (uint8_t *)data + data_size;
struct mesa_sha1 sha1_ctx;
blake3_hasher sha1_ctx;
_mesa_sha1_init(&sha1_ctx);
/* Hash the header with a zero SHA1 */