Commit graph

115447 commits

Author SHA1 Message Date
Roland Scheidegger
de1c89fd93 llvmpipe: fix CALLOC vs. free mismatches
Should fix some issues we're seeing. And use REALLOC instead of realloc.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2019-09-06 18:31:34 +02:00
Samuel Pitoiset
0bf51b6941 radv/gfx10: determine the number of vertices per primitive for TES
This doesn't fix anything known but it's correct now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 17:36:49 +02:00
Rhys Perry
bcd14756ee nir/lower_io_to_vector: add flat mode
This has lower_io_to_vector try to turn variables into arrays of 4-sized
vectors when possible and fall back to the old approach when that isn't
possible.

This is so that lower_io_to_vector can guarantee that only one variable is
used for each fragment shader output.

v2: handle dual-source blending
v3: don't try to merge structs and non-32-bit types in get_flat_type()
v3: fix per-vertex inputs
v3: fix and cleanup location advancement in get_flat_type() and it's
    calling code
v4: prioritize the original mode over the flat mode
v4: don't create flat variables to merge only one variable
v5: don't skip an entire slot when encountering structs in the old mode

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-06 15:38:04 +00:00
Rhys Perry
300e758b7c nir/lower_io_to_vector: allow FS outputs to be vectorized
v2: handle dual-source blending
v3: use a higher MAX_SLOTS

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-06 15:38:04 +00:00
Samuel Pitoiset
c6be5cefba radv/gfx10: make use the output usage mask when exporting NGG GS params
It shouldn't matter much because output varyings should have been
compacted during NIR shader linking but it mirrors what the driver
does when emitting NGG GS vertex parameters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 17:25:28 +02:00
Samuel Pitoiset
b1a872f0c0 radv/gfx10: account for the subpass view for the NGG GS storage
If the fragment shader needs the layer index, we have to allocate
one more dword in the NGG GS storage. Found by inspection. This
doesn't fix anything known.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 17:25:28 +02:00
Tomeu Vizoso
0efc0f8edc panfrost/ci: Increase timeouts
Sometimes LAVA jobs will timeout due to transient issues, and the Gitlab
job will fail in that case. Increase the timeouts to reduce the
likeliness of that happening and reduce false positives.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-06 16:35:16 +02:00
Tomeu Vizoso
8a5dd61828 panfrost/ci: Use special runner for LAVA jobs
So repositories don't need to be specially configured with a token to
access LAVA, store this token in a bind volume for a special runner.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-06 16:35:16 +02:00
Tomeu Vizoso
10b60dbd2c panfrost/ci: Re-add support for armhf
Now that Volt supports armhf, build again images and submit to LAVA for
RK3288.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-09-06 16:35:16 +02:00
Samuel Pitoiset
f31fb33432 radv: calculate esgs_itemsize in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:24 +02:00
Samuel Pitoiset
7fa00e178f radv: calculate the GSVS vertex size in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:22 +02:00
Samuel Pitoiset
3e8bda66ae radv: gather primitive ID in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:20 +02:00
Samuel Pitoiset
1877e87f1e radv: gather layer in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:19 +02:00
Samuel Pitoiset
84b346eda9 radv: gather viewport in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:17 +02:00
Samuel Pitoiset
d21489d415 radv: gather pointsize in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:09 +02:00
Samuel Pitoiset
a99d2d5564 radv: gather clip/cull distances in the shader info pass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:07 +02:00
Samuel Pitoiset
b16cf6c4c6 radv: move ac_fill_shader_info() to radv_nir_shader_info_pass()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:05 +02:00
Samuel Pitoiset
83499ac765 radv: merge radv_shader_variant_info into radv_shader_info
Having two different structs is useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 15:52:03 +02:00
Zhu, James
878439bba3 radeon: Fix mjpeg issue for ARCTURUS
ARCTURUS mjpeg is using direct register access.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2019-09-06 08:53:52 -04:00
Leo Liu
a3074370d9 radeon/vcn: add RENOIR VCN decode support
It has same VCN2.x block as Navi1x

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2019-09-06 08:53:52 -04:00
Danylo Piliaiev
aabde02f2f glsl: Fix unroll of do{} while(false) like loops
For loops which condition is false on the first iteration
iteration count was falsely calculated under the assumption
that loop's condition is true until it becomes false, meaning
it's true at least one time.
Now such loops are reported as having 0 iteration.

Similar to the fix e71fc7f2 done in NIR.

Fixes tests/shaders/glsl-fs-loop-while-false-02.shader_test

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-09-06 10:27:33 +00:00
Timur Kristóf
3debd0ef15 tgsi_to_nir: Remove dependency on libglsl.
This commit removes the GLSL dependency in TTN by manually recording
the textures used and calling nir_lower_samplers
instead of its GL counterpart.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-06 12:20:53 +03:00
Timur Kristóf
610cc3089c nir: Carve out nir_lower_samplers from GLSL code.
Lowering samplers is needed to produce NIR that can actually be
consumed by some gallium drivers, so it doesn't make sense to
to keep it only in the GLSL code.

This commit introduces nir_lower_samplers to compiler/nir,
while maintains the GL-specific function too.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2019-09-06 12:20:20 +03:00
Gert Wollny
9b9e1de90e radeonsi: Release storage for smda_uploads when the context is destroyed
This fixes a memory leak in the flush code:

Direct leak of 128 byte(s) in 1 object(s) allocated from:
    #0 in __interceptor_realloc .../gcc-8.3.0/libsanitizer/asan/asan_malloc_linux.cc:105
    #1 in si_buffer_do_flush_region src/gallium/drivers/radeonsi/si_buffer.c:573
    #2 in si_buffer_flush_region src/gallium/drivers/radeonsi/si_buffer.c:608
    #3 in si_buffer_flush_region src/gallium/drivers/radeonsi/si_buffer.c:597

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-06 09:44:24 +02:00
Mauro Rossi
7a6e7803a7 android: mesa: revert "Enable asm unconditionally"
This patch partially reverts 20294dc ("mesa: Enable asm unconditionally, ...")

Android makefile build logic needs to disable assembler optimization
in 32bit builds to avoid text relocations for libglapi.so shared

Fixes the following build error with Android x86 32bit target:

[  0% 4/477] target SharedLib: libglapi (out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so)
FAILED: out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so
...
prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld: warning: shared library text segment is not shareable
prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld: error: treating warnings as errors
clang-6.0: error: linker command failed with exit code 1 (use -v to see invocation)

Fixes: 20294dc ("mesa: Enable asm unconditionally, now that gen_matypes is gone.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-09-06 08:48:28 +02:00
Samuel Pitoiset
fa13b2f002 radv/gfx10: always set ballot_mask_bits to 64
The codegen handles it and it adds the correct casts. This fixes
a bunch of LLVM validation errors when enabling Wave32 for compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-06 08:11:43 +02:00
Caio Marcelo de Oliveira Filho
c0c55bd84f nir/lower_explicit_io: Handle 1 bit loads and stores
Load a 32-bit value then convert to 1-bit.  Convert 1-bit to 32-bit
value, then Store it.

These cases started to appear when we changed Anvil to use derefs for
shared memory.

v2: Use `bit_size` in a couple of places we were missing.  (Jason)
    Reassign `value` instead of `src[0]`.  (Jason)

Fixes: 024a46a407 ("anv: use derefs for shared memory access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-09-05 22:24:09 -07:00
Jason Ekstrand
d15fe8ca82 Revert "intel/fs: Move the scalar-region conversion to the generator."
This reverts commit c0504569ea.  Now that
we're doing interpolation lowering in NIR, we can continue to stride the
FS input registers directly in the brw_fs_nir code like we did before.
This fixes SIMD32 fragment shaders which broke because lower_simd_width
depended on the 0 stride to split PLN instructions correctly.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2019-09-06 03:58:09 +00:00
Jason Ekstrand
47e9743547 intel/fs: Fix FB write inst groups
This commit does two things.  First, it simplifies the way we compute
the FB write group bit.  There's no reason to use a ternary because
inst->group / 16 can only be 0 or 1.  Second, it fixes an order-of-
operations bug where the ternary wasn't selecting between (1 << 11) and
0 but between (1 << 11) and 0 | brw_dp_write_desc(...).

Fixes: 0d9648416 "intel/compiler: Use generic SEND for Gen7+ FB writes"
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-09-06 03:58:09 +00:00
Vasily Khoruzhick
aa77fc309a lima/ppir: don't lower phis to scalar
Utgard PP is vec4 architecture, so lowering phis to scalars
increases instruction count and potentially interferes with
spilling.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-05 19:29:16 -07:00
Jonathan Marek
feea5986a9 freedreno/a2xx: formats update
For render formats, update fd2_pipe2color to only work with HW supported
render formats, and remove the format whitelist is_format_supported. This
patch enables float render formats (which work).

For vertex/texture formats, use a generic function which translates using
the bitsize of the channels. Since we fake support for some vertex formats,
check for these in is_format_supported to avoid enabling them as sampler
formats.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-09-06 02:24:29 +00:00
Jonathan Marek
21dfa8e486 freedreno/a2xx: fix depth gmem restore
Use fd_gmem_restore_format() to avoid trying to use unsupported Z24S8/Z16
render formats for gmem restore.

Also apply this change to gmem2mem so it doesn't depend on fd2_pipe2color
working with depth formats.

gmem2mem/mem2gmem also doesn't need to use the swap/swizzle, since dst/src
formats are the same.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-09-06 02:24:29 +00:00
Jonathan Marek
88ca73bcd0 freedreno/a2xx: implement polygon offset
Fixes failures in the following deqp tests:
dEQP-GLES2.functional.polygon_offset.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
ac4ca24c32 freedreno/a2xx: fix SRC_ALPHA_SATURATE for alpha blend function
Fixes failures in the following deqp tests:
dEQP-GLES2.functional.fragment_ops.*src_alpha_saturate*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
80906a12d9 freedreno/a2xx: ir2: update register state in scalar insert
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-09-06 02:24:29 +00:00
Jonathan Marek
588cfe4a2b freedreno/a2xx: ir2: fix incorrect instruction reordering
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
2019-09-06 02:24:29 +00:00
Jonathan Marek
a6ebd4ab08 freedreno/a2xx: ir2: check opcode on the right instruction in export cp
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
19e62fec60 freedreno/a2xx: ir2: fix saturate in cp
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
c5e6961a58 freedreno/a2xx: ir2: set lower_fdph
The fdph opcode is not supported.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
22799787b5 freedreno/a2xx: ir2: remove pointcoord y invert
Fixes the following deqp test:
dEQP-GLES2.functional.shaders.builtin_variable.pointcoord

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Jonathan Marek
3516a90ab4 freedreno/a2xx: ir2: fix lowering of instructions after float lowering
Some instructions generated by int/bool float lowering need to be lowered
by opt_algebraic.

Fixes: 43dbd7d6

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 02:24:29 +00:00
Vasily Khoruzhick
517b60dc13 lima/ppir: don't lower vector {b,f}csel to scalar if condition is scalar
Utgard PP has vector fcsel operation, but its condition is scalar. Add
filtering callback that checks whether {b,f}csel condition is not scalar
to lower {b,f}csel to scalar only in this case.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-06 01:51:28 +00:00
Vasily Khoruzhick
9367d2ca37 nir: allow specifying filter callback in lower_alu_to_scalar
Set of opcodes doesn't have enough flexibility in certain cases. E.g.
Utgard PP has vector conditional select operation, but condition is always
scalar. Lowering all the vector selects to scalar increases instruction
number, so we need a way to filter only those ops that can't be handled
in hardware.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-09-06 01:51:28 +00:00
Rob Clark
f9f7cbc1aa util: android logging support
In particular, it would be nice for failed debug_assert() msgs to show
up in logcat.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-09-06 00:45:11 +00:00
Rob Clark
9baa72b7fc freedreno/ir3: allow copy propagation for relative
This appears to work fine (with the additional constraint of keeping the
indirect load in the same block that a0.x was loaded).

We can probably lift this restriction on earlier gens after testing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00
Rob Clark
d9ad6f54dc freedreno/ir3: fix cp cmps.s opt
Need to use ir3_instr_set_address(), otherwise the instruction might not
get added to the indirects table.  This becomes a problem when we turn
on copy propagation for relative accesses, as check_instr() in the sched
pass won't realize there is an indirect consumer of address register
load that is ready to be scheduled.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00
Rob Clark
e59bfc820b freedreno/ir3: assert that only single address
An instruction can reference only a single address register value.
Add an assert to catch bugs.

Also, address value should also be local to the same block as the
instruction.

(The one spot where changing the instruction address is actually legit
needs to clear the address first.)

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00
Rob Clark
f94f22e87a freedreno/ir3: fix mad copy propagation special case
After the next patch enabling copy propagation for relative sources,
we'll need to dereference the n'th src in valid_flags(), so we actually
need to swap the sources before calling valid_flags().

But the logic was already a bit cumbersome, so move it into a helper
function.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00
Rob Clark
1fd6a91d4a freedreno/ir3: fix addr/pred spilling
The live_values and use_count was not being properly updated.  This
starts triggering problems with the next patch, where we allow copy
propagation for RELATIV access.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00
Rob Clark
50a91fbf87 freedreno/ir3: cleanup "partially const" ubo srcs
Move the constant part of the indirect offset into nir intrinsic base.
When we have multiple indirect accesses with different constant offsets,
this lets other opt passes clean up things to use a single address
register value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-06 00:13:44 +00:00