Commit graph

115447 commits

Author SHA1 Message Date
Alyssa Rosenzweig
b4b2e111f8 pan/midgard: Link exit block
The exit block has been 'dangling' in the successors graph, so let's
ensure it's linked in.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-19 08:32:17 -07:00
Alyssa Rosenzweig
07c960cac0 pan/midgard: Add mir_exit_block helper
The exit block is gauranteed to be empty, signaling the end of the
program.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-19 08:32:17 -07:00
Alyssa Rosenzweig
aeeeef1242 pan/midgard: Maintain block predecessor set
While we already compute the successors array, for backwards data flow
analysis, it is useful to walk the control flow graph backwards based on
predecessors, so let's compute that information as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-19 08:32:17 -07:00
Alyssa Rosenzweig
4fa09329c1 pan/midgard: Use ralloc on ctx/blocks
This will allow us to get some level of automatic memory management.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-19 08:32:17 -07:00
Alyssa Rosenzweig
b59b1793b8 pan/midgard: Shrink successors[] to 2 length
A block can't have more.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-19 08:32:17 -07:00
Roman Stratiienko
fdd6151612 nir: Add missing dependency in Android.nir.gen.mk
Fixes incremental build with Android

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-19 09:53:18 +03:00
Erico Nunes
99d5bdcfa5 meson: build lima tools as part of 'all' tools
This is primarily so that this build gets tested in CI and we don't
break it again.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-08-18 22:27:55 +02:00
Connor Abbott
c550d367a7 ac/nir: Fix store_scratch with a non-full writemask
By adding one more helper to ac_llvm_build, we can also easily keep
vector stores together.

Fixes the
tests/spec/glsl-1.30/execution/fs-large-local-array-vec4.shader_test
piglit test.

Fixes: 74470baebb ("ac/nir: Lower large indirect variables to scratch")
Reviewed-by: Marek Olšák <marek.olsak@amd.com
2019-08-18 15:15:45 +02:00
Vasily Khoruzhick
0e394cda0d glsl/standalone: init shader stage in init_gl_program()
Otherwise lima standalone compiler fails when trying to compile fragment
shader with:

lima_compiler: ../src/compiler/nir/nir.c:55: nir_shader_create: Assertion `si->stage == stage' failed

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-08-17 11:14:40 -07:00
Jason Ekstrand
16edd02bfa iris: Only request an input mask if the shader needs it
Fixes: aebca3961b "iris: Fix handling of SIMD32 fragment shaders"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-16 19:59:42 -05:00
Xiong, James
dcad15ff54 gallium: add back YVU support
PIPE_FORMAT_YV12 is not handled so switching to PIPE_FORMAT_IYUV and
adding back YVU support.

Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-16 13:24:49 -07:00
Erico Nunes
7a51abab42 lima: actually wait for bo in lima_bo_wait
PIPE_TIMEOUT_INFINITE is unsigned and gets assigned to signed fields
where it ends up as -1. When this reaches the kernel as a timeout it
gets translated as no timeout, which cause the waiting functions to
return immediately and not actually wait for a completion.

This seems to cause unstable results with lima where even piglit tests
randomly fail.

Handle this by setting the signed max value in case of infinite timeout.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-08-16 16:31:29 +02:00
Rhys Perry
0a790c3019 nir/algebraic: add a few masking-before-unpack optimizations
Helps some Dawn of War 3 and F1 2017 shaders with ACO:
Totals from affected shaders:
SGPRS: 2136 -> 2128 (-0.37 %)
VGPRS: 1624 -> 1628 (0.25 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 168068 -> 164332 (-2.22 %) bytes
LDS: 44 -> 44 (0.00 %) blocks
Max Waves: 222 -> 221 (-0.45 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-16 12:13:01 +01:00
Vasily Khoruzhick
861c2b8d31 lima: fix compilation of standalone compiler
Fixes: e0aeee946004("lima: add summary report for shader-db")
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2019-08-15 16:59:51 -07:00
Bas Nieuwenhuizen
b9fb90e6d3 Revert "radv/gfx10: Enable DCC for storage images."
Quite useless without DCC for LAYOUT_GENERAL.

Fixes: b4dad3afaa Revert "radv: Do not decompress on LAYOUT_GENERAL."
Acked-by: Dave Airlie <airlied@redhat.com>
2019-08-16 01:22:54 +02:00
Bas Nieuwenhuizen
b4dad3afaa Revert "radv: Do not decompress on LAYOUT_GENERAL."
Causes issues with a bunch of games with DXVK.

Fixes: 50add1b33a "radv: Do not decompress on LAYOUT_GENERAL."
Acked-by: Dave Airlie <airlied@redhat.com>
2019-08-16 01:22:35 +02:00
Dave Airlie
f3af7886fe mesa: add support for CET to x86/x86-64 asm files.
Control-flow enforcement technology is a new instructions on x86
processors to denote where indirect jumps can land. Gcc auto adds
the instruction (which encodes as a NOP on older CPUs) to entrypoints
but assembler files need manual adding. This adds it to all the
entry points in the mesa x86/x86-64 assembler files.

This will only happen if mesa is built with the -fcf-protection flag
to gcc as some distros are wanting to do.

Acked-by: Eric Anholt <eric@anholt.net>
2019-08-16 09:00:35 +10:00
Alyssa Rosenzweig
78eda70892 pan/bifrost: Manually constant fold register class
Fixes errors for some people building Mesa:

../src/panfrost/bifrost/bifrost_sched.c:32:31: error: initializer
element is not constant
 const unsigned max_vec2_reg = max_primary_reg / 2;

../src/panfrost/bifrost/bifrost_sched.c:33:31: error: initializer
element is not constant
 const unsigned max_vec3_reg = max_primary_reg / 4; // XXX: Do we need
to align vec3 to vec4 boundary?

../src/panfrost/bifrost/bifrost_sched.c:34:31: error: initializer
element is not constant
 const unsigned max_vec4_reg = max_primary_reg / 4;

../src/panfrost/bifrost/bifrost_sched.c:35:32: error: initializer
element is not constant
 const unsigned max_registers = max_primary_reg +

../src/panfrost/bifrost/bifrost_sched.c:40:28: error: initializer
element is not constant
 const unsigned vec2_base = primary_base + max_primary_reg;

../src/panfrost/bifrost/bifrost_sched.c:41:28: error: initializer
element is not constant
 const unsigned vec3_base = vec2_base + max_vec2_reg;

../src/panfrost/bifrost/bifrost_sched.c:42:28: error: initializer
element is not constant
 const unsigned vec4_base = vec3_base + max_vec3_reg;

../src/panfrost/bifrost/bifrost_sched.c:43:27: error: initializer
element is not constant
 const unsigned vec4_end = vec4_base + max_vec4_reg;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-15 19:06:35 +00:00
Erik Faye-Lund
18ab42644b gallium/util: widen type before multiplication
This method returns size_t, but the multiplication multiplies two
integers, leading to overflow rather than type widening.

Noticed by compiling with MSVC, which emits a warning.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:53 +02:00
Erik Faye-Lund
0091f62978 mesa: avoid warning on Windows
On Windows, p_atomic_inc_return returns an unsigned long long rather
than the type the pointer refers to, so let's make sure we cast the
result to the right type. Otherwise, we'll trigger a warning about
the wrong format-string for the type.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:49 +02:00
Erik Faye-Lund
544b088616 win32: unify strcasecmp definitions
There was two incompatible definitions of strcasecmp, which lead to a
compiler warning. Let's clean this up by only leaving one of them, and
using that one all the time.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:44 +02:00
Erik Faye-Lund
ecd312be96 mesa/main: avoid warning when casting offset to pointer
This generates a warning on some 64-bit systems, so let's cast to a
properly sized integer first.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:39 +02:00
Erik Faye-Lund
c646cd4bac nir: avoid warning when casting bogus pointer
This intentionally-bogus pointer generates a warning on some 64-bit
systems, so let's cast to a properly-sized integer first.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:35 +02:00
Erik Faye-Lund
b355eef920 glsl: fixup u64-warning
Similarly to the unsigned-version, we need to first cast the result to a
suiting integer before negating the number, otherwise we'll trigger a
warning.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-15 20:23:13 +02:00
Kenneth Graunke
f741de236b isl: Enable Unorm Path in Color Pipe
Improves performance on my Icelake 8x8 locked to 700Mhz.  For example,
some GfxBench5 subtests have the following results:

- [i965] gl_manhattan: ................ 7.01119% +/- 0.180971% (n=5)
- [i965] gl_4 (Car Chase):              4.24351% +/- 0.175622% (n=5)
- [i965] gl_blending:  ................ 3.36327% +/- 0.180267% (n=5)
- [i965] gl_5_normal (Aztec Ruins):     1.67962% +/- 0.243534% (n=10)
- [iris] gl_manhattan: ................ 3.92357% +/- 0.073965% (n=25)
- [iris] gl_4 (Car Chase):              2.17746% +/- 0.0826858% (n=5)
- [iris] gl_blending:  ................ 2.79599% +/- 0.803652% (n=15)
- [iris] gl_5_normal (Aztec Ruins):     1.30930% +/- 0.106523% (n=25)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-15 10:39:09 -07:00
Rafael Antognolli
ceeaf93c8e anv: Properly initialize device->slice_hash.
When subslices_delta == 0 and we take the early return,
device->slice_hash is not initialized on GEN11. It then causes a
segfault when going through anv_DestroyDevice, if compiled with
valgrind.

Fixes: 7bc022b4bb ("anv/gen11: Emit SLICE_HASH_TABLE when pipes are
                    unbalanced.)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-15 09:42:48 -07:00
Danylo Piliaiev
72354d43d4 intel/compiler: Fix resource leak in error path
CID: 1452261

Fixes: 04a99515 "intel/compiler: add ability to override shader's assembly"

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-08-15 08:17:36 +00:00
Alyssa Rosenzweig
44a6c38bd6 panfrost: Implement native RECT textures
We started honouring the normalized_coords flag in the texture
descriptor, but a bisection revealed that broke RECT textures -- since
we were *also* lowering them in the shader. So just remove the
shader-based lowering, use native RECT textures, and enjoy the nominal
reduction in complexity and performance boost.

Fixes: 3e47a1181b ("panfrost: Add MALI_SAMP_NORM_COORDS flag")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:42 -07:00
Alyssa Rosenzweig
6fe4822cca panfrost: Add R10G10B10A2_SSCALED vertex format
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
e823a47f02 pan/midgard: Disassemble UBO index explicitly
It's a bit of a special case but that's fine.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
3d54ed2488 pan/midgard: Account for unaligned UBOs when promoting uniforms
We only know how to promote aligned accesses, although theoretically we
should be able to promote unaligned to swizzles in the future. Check
this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
03350eb8b8 pan/midgard: Add mir_ubo_shift helper
Different UBO reads have different shift requirements.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
cf3bb10f51 pan/midgard: Address emit_ubo_read offset in bytes
We'll want to be smarter about unaligned reads, so let's get this code
all in one place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
65e6cb4eb0 pan/midgard: Wire writemask into UBO reads
Helps the disassembly be clearer and maybe regalloc be smarter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
ec2f0b580f pan/midgard: Identify UBO/SSBO op symmetry
It's the same thing, just shifted.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:57:24 -07:00
Alyssa Rosenzweig
375d4c2c74 panfrost: Extend blending to MRT
Our hardware supports independent (per-RT) blending, but we need to
route those settings through from Gallium.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:40 -07:00
Alyssa Rosenzweig
dff4986b1a pan/midgard: Emit store_output branch just-in-time
We'll need multiple branches for MRT, so we can't defer. Also, we need
to track dependencies to ensure r0 is set to the correct value for each
store_output.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:40 -07:00
Alyssa Rosenzweig
2fc44c4dc8 pan/midgard: Add dont_eliminate flag
We need to treat fragment writes specially.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:40 -07:00
Alyssa Rosenzweig
6ed3843224 pan/mfbd: Stuff in RT count
Fixes DATA_INVALID_FAULTs with multiple render targets.

We do always allocate space for 4 cbufs just to keep things sane. This
may not be strictly necessary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:40 -07:00
Alyssa Rosenzweig
716be7862e pan/decode: Dump FBD tagged pointer
Turns out the rt count is stuffed in here..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:40 -07:00
Alyssa Rosenzweig
358372b256 pan/decode: Decode invalid access type upon fault
We don't have a good way to confirm this, but it parallels the kernel
definitons for MMU faults nicely.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:39 -07:00
Alyssa Rosenzweig
f5cc5ef404 pan/decode: Fix duplicate heap_end property
This was supposed to read heap_start. It's the same value but still,
better get this right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:42:39 -07:00
Alyssa Rosenzweig
b78e04c17b panfrost: Note "MFBD preload disable" bit
It's a chicken bit, as far as I can tell. Buck buck.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 16:39:57 -07:00
Alyssa Rosenzweig
64720d1e9e pan/bifrost: Link in compiler
We enable the standalone compiler, build the new files, and let it
blast.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
b93fa7d232 pan/bifrost: Check in remainder of the Bifrost compiler
What it says on the tin.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
0e126aa0f0 pan/bifrost: Add bifrost_print.c/h
IR printers.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
d8d8b08fe5 pan/bifrost: Style format the disassembler
$ astyle *.c *.h --style=linux -s8

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
fca491c0e1 pan/bifrost: Stub out standalone compiler
We don't actually have a standalone compiler in-tree yet, but let's get
prepared for when we do.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
62bbc23da5 pan/bifrost: Sync disassembler with Ryan's tree
The disassembler was updated to move common code with the compiler into
a shared header. Additional, some new ops and control registers relating
to rounding were added.

Signed-off-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 22:54:07 +00:00
Alyssa Rosenzweig
b73cbd6880 panfrost: Remove standalone pandecode tool
Now that panwrap has gained the ability to trace directly without
dumping to the filesystem, there's no need to lug around this tool.

I can assure you nobody will miss it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-14 15:09:17 -07:00