Commit graph

39920 commits

Author SHA1 Message Date
Thomas Hellstrom
893620e52e st/xorg: Fix typo
Pointed out by Jakob Bornecrantz.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 18:26:05 +02:00
Brian Paul
f1c1ee11d3 ir_to_mesa: assorted clean-ups, const qualifiers, new comments 2010-10-12 09:26:54 -06:00
José Fonseca
6fbd4faf97 gallivm: Name anonymous union. 2010-10-12 16:08:09 +01:00
Brian Paul
0ad9d8b538 st/xlib: add some comments 2010-10-12 08:54:54 -06:00
Brian Paul
3633e1f538 glsl2: fix signed/unsigned comparison warning 2010-10-12 08:54:16 -06:00
José Fonseca
e3ec0fdd54 llmvpipe: improve mm_mullo_epi32
Apply Jose's suggestions for a small but measurable improvement in
isosurf.
2010-10-12 14:17:21 +01:00
Thomas Hellstrom
b6b7ce84e5 st/xorg: Don't try to remove invalid fbs
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 15:09:05 +02:00
Thomas Hellstrom
201c3d3669 xorg/vmwgfx: Don't hide HW cursors when updating them
Gets rid of annoying cursor flicker

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 15:09:05 +02:00
Thomas Hellstrom
bfd065c71e st/xorg: Add a customizer option to get rid of annoying cursor update flicker
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 15:09:05 +02:00
Thomas Hellstrom
f0bbf130f9 xorg/vmwgfx: Make vmwarectrl work also on 64-bit servers
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 15:09:04 +02:00
Thomas Hellstrom
ec08047a80 st/xorg: Don't try to use option values before processing options
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2010-10-12 15:09:04 +02:00
Keith Whitwell
0ca0382d1b Revert "llvmpipe: try to keep plane c values small"
This reverts commit 9773722c2b.

Looks like there are some floor/rounding issues here that need
to be better understood.
2010-10-12 13:20:39 +01:00
Keith Whitwell
22ec25e2bf gallivm: don't branch on KILLs near end of shader 2010-10-12 13:14:51 +01:00
Keith Whitwell
d0eb854f58 r600g: add missing file to sconscript 2010-10-12 13:08:34 +01:00
Keith Whitwell
1a574afabc gallium: move sse intrinsics debug helpers to u_sse.h 2010-10-12 13:02:28 +01:00
José Fonseca
39331be44e llvmpipe: Fix MSVC build.
MSVC doesn't accept more than 3 __m128i arguments.
2010-10-12 12:27:55 +01:00
Keith Whitwell
b4277bc584 llvmpipe: fix typo in last commit 2010-10-12 11:52:39 +01:00
Keith Whitwell
9773722c2b llvmpipe: try to keep plane c values small
Avoid accumulating more and more fixed point bits.
2010-10-12 11:50:14 +01:00
Keith Whitwell
9d59e148f8 llvmpipe: add debug helpers for epi32 etc 2010-10-12 11:50:13 +01:00
Keith Whitwell
2cf98d5a6d llvmpipe: try to do more of rast_tri_3_16 with intrinsics
There was actually a large quantity of scalar code in these functions
previously.  This tries to move more into intrinsics.

Introduce an sse2 mm_mullo_epi32 replacement to avoid sse4 dependency
in the new rasterization code.
2010-10-12 11:50:07 +01:00
José Fonseca
4cb3b4ced8 llvmpipe: Do not dispose the execution engine.
The engine is a global owned by gallivm module.
2010-10-12 08:36:51 +01:00
Francisco Jerez
c25fcf5aa5 nouveau: Get larger push buffers.
Useful to amortize the command submission/reloc overhead (e.g. etracer
goes from 72 to 109 FPS on nv4b).
2010-10-12 04:13:22 +02:00
Francisco Jerez
70828aa246 dri/nouveau: Initialize tile_flags when allocating a render target. 2010-10-12 04:12:56 +02:00
Dave Airlie
965f69cb0c r600g: fix typo in vertex sampling on r600
fixes https://bugs.freedesktop.org/show_bug.cgi?id=30771

Reported-by: Kevin DeKorte
2010-10-12 09:45:22 +10:00
Eric Anholt
bcec03d527 i965: Always use the new FS backend on gen6.
It's now much more correct for gen6 than the old backend, with just 2
regressions I've found (one of which is common with pre-gen6 and will
be fixed by an array splitting IR pass).

This does leave the old Mesa IR backend getting used still when we
don't have GLSL IR, but the plan is to get GLSL IR input to the driver
for the ARB programs and fixed function by the next release.
2010-10-11 15:32:41 -07:00
Eric Anholt
0cadd32b6d i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.
Pre-gen6, you could mix int and float just fine.  Now, you get goofy
results.

Fixes:
glsl-arb-fragment-coord-conventions
glsl-fs-fragcoord
glsl-fs-if-greater
glsl-fs-if-greater-equal
glsl-fs-if-less
glsl-fs-if-less-equal
2010-10-11 15:26:59 -07:00
Eric Anholt
17306c60ad i965: Don't compute-to-MRF in gen6 VS math.
There was code to do this for pre-gen6 already, this just enables it
for gen6 as well.
2010-10-11 15:26:59 -07:00
Eric Anholt
720ed3c906 i965: Expand uniform args to gen6 math to full registers to get hstride == 1.
This is a hw requirement in math args.  This also is inefficient, as
we're calculating the same result 8 times, but then we've been doing
that on pre-gen6 as well.  If we're doing math on uniforms, though,
we'd probably be better served by having some sort of mechanism for
precalculating those results into another uniform value to use.

Fixes 7 piglit math tests.
2010-10-11 15:26:58 -07:00
Eric Anholt
317dbf4613 i965: Don't compute-to-MRF in gen6 math instructions. 2010-10-11 15:26:58 -07:00
Eric Anholt
7b5bc38c44 i965: Add a couple of checks for gen6 math instruction limits. 2010-10-11 15:26:58 -07:00
Eric Anholt
25cf241540 i965: Don't consider gen6 math instructions to write to MRFs.
This was leftover from the pre-gen6 cleanups.  One tests regresses
where compute-to-MRF now occurs.
2010-10-11 15:26:58 -07:00
Chad Versace
41c2079855 glsl: Changes in generated file glsl_lexer.cpp
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
2010-10-11 14:25:53 -07:00
Chad Versace
0c9fef6111 glsl: Add lexer rules for uint and uvecN (N=2..4)
Commit for generated file glsl_lexer.cpp follows this commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2010-10-11 14:25:48 -07:00
Chad Versace
fc99a3beb9 glsl: Add glsl_type::uvecN_type for N=2,3
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2010-10-11 14:25:44 -07:00
Chad Versace
a34817917b intel_extensions: Add ability to set GLSL version via environment
Add ability to set the GLSL version used by the GLcontext by setting the
environment variable INTEL_GLSL_VERSION. For example,
    env INTEL_GLSL_VERSION=130 prog args
If the environment variable is missing, the GLSL versions defaults to 120.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2010-10-11 14:25:30 -07:00
Daniel Vetter
603741a86d r200: revalidate after radeon_update_renderbuffers
By calling radeon_draw_buffers (which sets the necessary flags
in radeon->NewGLState) and revalidating if NewGLState is non-zero
in r200TclPrimitive. This fixes an assert in libdrm (the color-/
depthbuffer was changed but not yet validated) and and stops the
kernel cs checker from complaining about them (when they're too
small).

Thanks to Mario Kleiner for the hint to call radeon_draw_buffer
(instead of my half-broken hack).

v2: Also fix the swtcl r200 path.

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-10-11 15:16:44 -04:00
Eric Anholt
c6dbf253d2 i965: Compute to MRF in the new FS backend.
This didn't produce a statistically significant performance difference
in my demo (n=4) or nexuiz (n=3), but it still seems like a good idea
and is recommended by the HW team.
2010-10-11 12:08:13 -07:00
Eric Anholt
06fd639c51 i965: Give the FB write and texture opcodes the info on base MRF, like math. 2010-10-11 12:07:33 -07:00
Eric Anholt
0cd6cea8a3 i965: Give the math opcodes information on base mrf/mrf len.
This is progress towards enabling a compute-to-MRF pass.
2010-10-11 12:03:34 -07:00
Eric Anholt
37758fb1cb i965: Move FS backend structures to a header.
It's time to start splitting some of this up.
2010-10-11 11:52:02 -07:00
Eric Anholt
251fe27854 i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.
While I don't know of any performance changes from this (once extra
reg available out of 128), it makes the generated asm a lot cleaner
looking.
2010-10-11 11:52:01 -07:00
Eric Anholt
90c4022040 i965: Split FS_OPCODE_DISCARD into two steps.
Having the single opcode write then read the reg meant that single
instruction opcodes had to consider their source regs to interfere
with their dest regs.
2010-10-11 11:52:01 -07:00
José Fonseca
986cb9d5cf llvmpipe: Use lp_tgsi_info. 2010-10-11 13:06:25 +01:00
José Fonseca
7c1b5772a8 gallivm: More detailed analysis of tgsi shaders.
To allow more optimizations, in particular for direct textures.
2010-10-11 13:05:32 +01:00
José Fonseca
11dad21718 tgsi: Export some names for some tgsi enums.
Useful to give human legible names in other cases.
2010-10-11 13:05:31 +01:00
José Fonseca
6c1aa4fd49 gallium: Define C99 restrict keyword where absent. 2010-10-11 13:05:31 +01:00
José Fonseca
e1003336f0 gallivm: Eliminate unsigned integer arithmetic from texture coordinates.
SSE support for 32bit and 16bit unsigned arithmetic is not complete, and
can easily result in inefficient code.

In most cases signed/unsigned doesn't make a difference, such as for
integer texture coordinates.

So remove uint_coord_type and uint_coord_bld to avoid inefficient
operations to sneak in the future.
2010-10-11 08:14:09 +01:00
José Fonseca
b18fecbd0e llvmpipe: Remove outdated comment about stencil testing. 2010-10-11 08:14:09 +01:00
Dave Airlie
3322416de4 r600g: don't run with scissors.
This could probably be done much nicer, I've spent a day chasing
a coherency problem in the kernel, that turned out to be incorrect
scissor setup.
2010-10-11 16:23:23 +10:00
Dave Airlie
ef2702fb20 r600g: add TXL opcode support.
fixes glsl1-2D Texture lookup with explicit lod (Vertex shader)
2010-10-11 12:18:05 +10:00